OFDM Symbol Interleaver Addressing for DVB-T2 4K Mode

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Solution Overview

Problem

DVB-T2 communication systems face challenges in improving data integrity due to correlated fading in terrestrial broadcast channels, which affects the performance of error correction coding schemes, particularly in separating encoded symbols across OFDM sub-carrier signals.

Innovation Solution

A symbol interleaver is implemented using a permutation code and generator polynomial, with an address generator that generates write and read addresses for the interleaver memory, optimizing the mapping of data symbols onto OFDM sub-carrier signals, and a de-interleaver in the receiver reverses this process to maintain data integrity across different modes like 1k, 2k, 4k, 8k, and 16k.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If symbol interleaving is implemented to separate encoded symbols across sub-carrier signals, then error correction performance is improved, but device complexity increases due to additional interleaver memory and address generation circuits

Engineering Contradiction:
Improveerror correction performanceVSAvoidinterleaver structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The address generator is designed to universally support multiple DVB-T modes (2k, 8k, and other modes) through a single unified structure. The generator uses mode selection inputs to configure the same hardware circuit for different sub-carrier counts, eliminating the need for separate address generators for each mode and reducing overall device complexity while maintaining error correction performance across all modes

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically changes parameters of the address generator based on the selected DVB-T mode. The mode selection input modifies the operation of the linear feedback shift register and permutation circuit to generate appropriate addresses for different sub-carrier configurations, allowing the same hardware to adapt to different interleaving requirements without physical reconfiguration

Inventive Principle:
Principle #35Parameter changes

2Reliability

If separate address generators are provided for each DVB-T mode (2k, 8k), then mode-specific optimization is achieved, but device complexity and resource usage increase

Engineering Contradiction:
Improvemode-specific performance optimizationVSAvoidnumber of address generators
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A single address generator circuit performs the function of multiple mode-specific generators by accepting a mode selection input. The generator reconfigures its internal logic (linear feedback shift register connections and permutation circuit behavior) based on the selected mode, providing optimized address sequences for 2k, 8k, and other modes without requiring separate dedicated circuits for each mode

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The address generator transitions from a static, mode-specific design to a dynamic, reconfigurable structure. The mode selection input enables the circuit to change its operational characteristics in real-time, adjusting the address generation algorithm to match the requirements of the currently active DVB-T mode, thereby achieving mode-specific optimization with a single dynamic component

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3582401B1Data processing apparatus and method
Publication Date: 2021.07.07 SATURN LICENSING LLC
  • EP3582401B1 patent drawingFigure 1
  • EP3582401B1 patent drawingFigure 2
  • EP3582401B1 patent drawingFigure 3

AI summary

A data processing apparatus maps symbols received from a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols into an output symbol stream. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of Riʹ10=Ri−1ʹ0⊕Ri−1ʹ2, and the permutation code forms, with an additional bit, a twelve bit address. The permutation code is changed from one OFDM symbol to another, thereby providing an improvement in interleaving the data symbols for a 4K operating mode of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial2 (DVB-T2). This is because there is a reduced likelihood that successive data bits which are close in order in an input data stream are mapped onto the same sub-carrier of an OFDM symbol.