OFDM Symbol Interleaver Using LFSR Addressing for Multi-Mode DVB
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Solution Overview
Problem
The existing DVB-T and DVB-H standards lack a 0.5k mode interleaver, which is necessary for more frequent channel estimation updates to accurately track time variations due to Doppler and other effects, and existing error correction coding schemes perform suboptimally due to correlated fading in terrestrial broadcast channels.
Innovation Solution
A data processing apparatus that maps input symbols onto OFDM sub-carrier signals using a linear feedback shift register and permutation circuit to generate pseudo-random bit sequences and addresses, allowing for flexible implementation across various modes, including 0.5k, 1k, 2k, 4k, 8k, 16k, and 32k, by adjusting the generator polynomial and permutation order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a symbol interleaver is provided for DVB-T and DVB-H standards, then data integrity is improved, but the standards lack a 0.5k mode interleaver which is necessary for more frequent channel estimation updates
Solution Approach 1:
The address generator is designed to support multiple OFDM modes (0.5k, 1k, 2k, 4k, 8k, 16k, and 32k modes) through a single unified structure. The linear feedback shift register and permutation circuit can be configured with different generator polynomials and permutation orders to accommodate various mode requirements, making the interleaver universally applicable across all DVB-T and DVB-H modes while enabling the previously missing 0.5k mode for more frequent channel estimation updates
2Productivity
If existing error correction coding schemes are used, then communication is maintained, but performance is suboptimal due to correlated fading in terrestrial broadcast channels
Solution Approach 1:
The symbol interleaver performs preliminary interleaving of data symbols onto OFDM sub-carrier signals before transmission. By using a carefully designed address generator with linear feedback shift register and permutation circuit, the interleaver distributes symbols across sub-carriers in a pattern that proactively separates correlated fading effects, ensuring that error correction coding schemes receive pre-processed data with reduced correlation, thereby improving both reliability and communication efficiency
3Reliability
If a linear feedback shift register and permutation circuit are used to generate pseudo-random bit sequences, then symbol separation is optimized, but device complexity increases
Solution Approach 1:
The patent replaces complex memory-based address generation methods with a streamlined linear feedback shift register and permutation circuit. Instead of using large lookup tables or complex random number generators, the system uses the mathematical properties of linear feedback shift registers with specific generator polynomials combined with permutation circuits to generate the required pseudo-random bit sequences. This substitution maintains optimal symbol separation quality while significantly reducing device complexity and computational requirements
Data Source
AI summary
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.