OFDM Interleaver Memory Addressing for Multi-Mode Sub-Carrier Mapping
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Solution Overview
Problem
Existing OFDM systems, such as DVB-T and DVB-T2, face challenges in efficiently managing the varying number of sub-carriers across different operating modes, leading to increased memory requirements for interleavers, which complicates the implementation of frequency interleaving and affects data integrity.
Innovation Solution
A data processing apparatus with a controller, address generator, and interleaver memory that operates in odd and even interleaving modes, determining valid addresses for each mode to minimize memory usage by using a single interleaver memory size equal to the maximum number of sub-carriers, allowing seamless transition between different OFDM symbol types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate interleaver memory is allocated for each operating mode, then the data mapping can be optimized for each mode, but the memory requirements and device complexity increase significantly
Solution Approach 1:
The patent implements a universal interleaver memory that serves all operating modes (2k, 8k, and intermediate modes). The single memory structure is controlled by a mode selection unit that configures the memory operation according to the active mode, eliminating the need for separate memory allocations while maintaining mode-specific optimization capabilities.
Solution Approach 2:
The patent employs dynamic configuration of the interleaver memory based on the operating mode. The mode selection unit dynamically adjusts the memory addressing and operation parameters according to the active mode (2k, 8k, or intermediate), allowing the same physical memory to adapt its behavior to different data mapping requirements without requiring separate static memory structures for each mode.
2Adaptability or versatility
If the number of sub-carriers varies across different OFDM modes, then the system can support multiple operating modes, but managing memory addresses becomes complex and error-prone
Solution Approach 1:
The patent implements a mode selection unit that receives feedback about the active operating mode and automatically configures the interleaver memory parameters accordingly. This feedback mechanism ensures that the memory addressing is always consistent with the current mode's sub-carrier configuration, eliminating address management errors while supporting multiple modes.
Solution Approach 2:
The patent changes the operational parameters of the interleaver memory based on the active mode. The mode selection unit adjusts memory size, addressing scheme, and other parameters according to whether the system is operating in 2k, 8k, or intermediate mode, allowing flexible adaptation to different sub-carrier configurations without manual reconfiguration.
3Adaptability or versatility
If intermediate modes between 2k and 8k are introduced, then the system flexibility improves, but the existing address generation algorithms become insufficient
Solution Approach 1:
The patent extends the existing address generation algorithms to handle intermediate modes universally. The mode selection unit identifies when an intermediate mode is active and triggers the extended addressing logic, allowing the same hardware structure to generate correct addresses for 2k, 8k, and any intermediate modes without requiring separate address generation circuits for each mode.
Solution Approach 2:
The patent prepares the address generation logic in advance to handle all possible modes including intermediates. The mode selection unit pre-configures the addressing parameters based on the detected mode, so that when data mapping is performed, the correct addressing scheme is already in place, eliminating the need for complex real-time calculations during data transmission.
Data Source
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AI summary
A data processing apparatus is operable to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols include first sets of data symbols and second sets of input data symbols. The data processing apparatus includes a controller, an address generator and an interleaver memory. The controller is operable, when operating in accordance with an even interleaving process to read out a first set of the input data symbols from the interleaver memory on to the sub-carrier signals of an even OFDM symbol using read addresses generated by the address generator, and to write in a second set of the input data symbols into the interleaver memory using the addresses generated by the address generator. The controller is operable in accordance with an odd interleaving process, to read out a first set of input data symbols from the interleaver memory on to the sub-carrier signals of an odd OFDM symbol using read addresses determined in accordance with a sequential order of the first set of input data symbols, and to write in a second set of the input data symbols into the interleaver memory at write addresses determined in accordance with the sequential order of the first group of input data symbols. The controller is operable to determine before reading out the first input data symbols from the interleaver memory, whether the read address is valid for a previous OFDM symbol, and to determine before writing the second input data symbols into the interleaver memory, whether the write address is valid for a current OFDM symbol. As such, the interleaver memory size can be minimised to an amount which corresponds to a maximum number of sub-carriers, which are available for an OFDM symbol for any of the operating modes. Application can be found with DVB-T2, which includes a 32K mode.