OFDM Interleaver Memory Bank Segmentation for Parallel Data Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional interleavers for OFDM transmitters based on IEEE 802.11 standards are inefficient due to the need for unnecessary data rearrangement and complex controller design, as they do not separately execute first and second permutation processes, and have memory access schemes that vary significantly with different mapping schemes.
Innovation Solution
The interleaving apparatus divides memory into independently controlled memory banks, allowing data to be written and read in parallel, and rearranges output data bits according to mapping schemes, separating first and second permutation processes to simplify data output and reduce unnecessary processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional interleavers execute both permutation processes without separation, then the device structure is simpler, but unnecessary data rearrangement occurs and processing efficiency deteriorates
Solution Approach 1:
The interleaver is divided into a first interleaver performing first permutation and a second interleaver performing second permutation. This segmentation allows each module to handle specific permutation tasks independently, eliminating unnecessary data rearrangement and improving processing efficiency without significantly increasing overall system complexity.
2Adaptability or versatility
If memory access schemes are designed for each mapping scheme, then adaptability to different standards is improved, but device complexity and design difficulty increase
Solution Approach 1:
The interleaver design uses universal permutation equations and control logic that can handle multiple mapping schemes (BPSK, QPSK, 16-QAM, 64-QAM) through parameter configuration rather than separate hardware designs. The same interleaver structure adapts to different standards by adjusting permutation parameters, reducing device complexity while maintaining broad adaptability.
3Productivity
If single memory structure is used, then device complexity is reduced, but data rearrangement efficiency and parallel processing capability deteriorate
Solution Approach 1:
The memory structure is segmented into multiple independent memory banks, each capable of parallel read/write operations. This segmentation enables simultaneous data access from multiple banks, achieving parallel processing capability and improving data rearrangement efficiency without requiring overly complex unified memory management.
Data Source
AI summary
An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation unit, and a second permutation and output selection unit. The memory unit includes a plurality of memory banks, which are capable of being independently controlled so that data can be written or read in/from the memory banks, each having memory cells arranged in an N×M matrix structure. The memory write/read control unit generates control signals to write/read data in/from the memory unit. The memory access address generation unit generates a memory access address used to write/read data in/from the memory unit in response to the memory write/read control signals. The second permutation and output selection unit rearranges the positions of data bits output from the memory unit and outputs the position-rearranged data bits.