OFDM Interleaver Memory Mapping for DVB-T2 8K Error Correction
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Solution Overview
Problem
Existing OFDM systems, such as DVB-T and DVB-H, face challenges in error correction due to correlated fading in terrestrial broadcast channels, which can be mitigated by effectively interleaving data symbols across sub-carrier signals, but current interleaving schemes are not optimal, especially for the 8K mode of DVB-T2.
Innovation Solution
A data processing apparatus with an interleaver memory and address generator using a linear feedback shift register and permutation circuit to generate addresses for interleaving data symbols, employing an odd interleaving process and cycling through different permutation codes to reduce the likelihood of successive data bits being mapped to the same sub-carrier, thereby improving error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data symbols are mapped directly onto sub-carrier signals without interleaving, then the mapping process is simple and fast, but error correction performance deteriorates due to correlated fading in terrestrial broadcast channels
Solution Approach 1:
The data symbols are segmented and distributed across multiple sub-carrier signals through interleaving. The address generator segments the mapping process by generating distinct addresses for different data symbols, ensuring they are placed on different sub-carriers. This segmentation approach separates encoded symbols by as much as possible, improving error correction performance while maintaining manageable complexity through systematic address generation.
Solution Approach 2:
The interleaving scheme employs dynamic address generation using a linear feedback shift register that changes the mapping positions adaptively. The address generator dynamically determines which sub-carrier receives which data symbol based on the current state of the shift register, creating a flexible mapping that optimizes error correction without requiring complex predefined interleaving patterns.
2Reliability
If a fixed permutation code is used for address generation, then the address generator is simple to implement, but successive data bits may be mapped to the same sub-carrier reducing interleaving effectiveness
Solution Approach 1:
The linear feedback shift register operates periodically, cycling through different address sequences. This periodic action ensures that successive data bits are mapped to different sub-carriers across multiple OFDM symbols. The shift register's natural periodic behavior provides effective interleaving without requiring complex external control logic, maintaining implementation simplicity while achieving reliable symbol separation.
3Quantity of substance
If the number of sub-carriers is increased to 8192 for 8K mode, then data transmission capacity is improved, but the effectiveness of existing interleaving schemes deteriorates
Solution Approach 1:
The address generator parameters are specifically optimized for 8K mode with 8192 sub-carriers. The linear feedback shift register is configured with appropriate polynomial and initial conditions to generate addresses that effectively distribute data symbols across the large number of sub-carriers. This parameter optimization ensures that the interleaving remains effective even when the total number of sub-carriers increases to 8192, maintaining reliable error correction performance.
Data Source
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AI summary
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of Riʹ11=Ri-1ʹ0⊕Ri-1ʹ1⊕Ri-1ʹ4⊕Ri-1ʹ6, and the permutation code forms, with an additional bit, a thirteen bit address. The address generator includes an offset generator which is operable to add an offset to the formed thirteen bit address, and the data processing apparatus is adapted to interleave the input data symbols in accordance with an odd interleaving process, thereby providing an improvement in interleaving the data symbols for an 8K operating mode of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial2 (DVB-T2). This is because there is a reduced likelihood that successive data bits which are close in order in an input data stream are mapped onto the same sub-carrier of an OFDM symbol.