OFDM Odd-Even Interleaving for Variable Sub-Carrier Modes

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Solution Overview

Problem

Existing OFDM systems, such as DVB-T and DVB-T2, face challenges in efficiently managing the varying number of sub-carriers across different operating modes, leading to increased memory requirements for interleavers, which complicates the implementation of frequency interleaving and affects data integrity.

Innovation Solution

A data processing apparatus that uses a controller, address generator, and interleaver memory to implement an odd-even interleaving scheme, where the number of sub-carriers is determined for each OFDM symbol, allowing for minimal memory usage by validating addresses before reading or writing data, and using a single memory block to accommodate the maximum number of sub-carriers across all modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a single interleaver memory is used to accommodate the maximum number of sub-carriers across all modes, then memory usage is minimized, but the complexity of managing varying sub-carrier numbers across different operating modes increases

Engineering Contradiction:
Improvememory sizeVSAvoidcomplexity of managing varying sub-carrier numbers
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The system dynamically adapts the interleaving process to different operating modes (2k, 8k, 32k) by adjusting the number of sub-carriers and corresponding memory addressing schemes. The controller dynamically determines whether to perform odd or even interleaving based on the current mode, allowing a single memory structure to handle varying sub-carrier counts without requiring mode-specific hardware configurations.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

A single interleaver memory block is designed to universally accommodate all operating modes by using mode-dependent addressing strategies. The same physical memory structure serves multiple functions across different modes (2k, 8k, 32k) by adjusting how addresses are generated and interpreted, eliminating the need for separate memory blocks for each mode.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If odd-even interleaving is implemented with dynamic mode switching, then data integrity is improved, but the processing time and control complexity increase

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary determination of the interleaving mode (odd or even) based on the current operating mode before actual data processing begins. The controller pre-establishes the appropriate addressing scheme and memory access pattern, so that when data processing occurs, no additional time is lost for mid-processing mode switches or address recalculations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes key parameters (number of sub-carriers, interleaving pattern, memory addressing scheme) based on the operating mode. By dynamically adjusting these parameters, the system optimizes data integrity for each mode while minimizing the time required for parameter reconfiguration, as the changes are prepared and applied systematically rather than ad hoc.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8175142B2Odd-even interleaving while changing the operating mode in a digital video broadcasting (DVB) standard
Publication Date: 2012.05.08 SONY GROUP CORP
  • US8175142B2 patent drawing
  • US8175142B2 patent drawing
  • US8175142B2 patent drawing

AI summary

A data processing apparatus to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols include first sets of data symbols and second sets of input data symbols. The data processing apparatus includes a controller, an address generator, and an interleaver memory. The controller is configured, when operating in accordance with an even interleaving process, to read out a first set of the input data symbols from the interleaver memory on to the sub-carrier signals of an even OFDM symbol using read addresses generated by the address generator, and to write in a second set of the input data symbols into the interleaver memory using the addresses generated by the address generator.