OFDM Symbol Interleaving Using Odd Mapping for Shared Memory
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Solution Overview
Problem
The existing DVB-T and DVB-H standards face challenges in providing an efficient implementation of symbol interleavers across various modes, which affects the performance and cost of data communication, particularly in DVB-T2, where the known interleaving schemes work better for odd symbols than even symbols, leading to suboptimal memory usage and inefficiency.
Innovation Solution
A data processing apparatus that uses an odd interleaving process for both odd and even symbols when the number of sub-carriers is less than half of the maximum, allowing for a single interleaver memory to handle both, reducing memory requirements and optimizing performance by using different parts of the memory for writing and reading data symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate odd and even interleaving processes are used for different OFDM symbols, then the interleaving performance is optimized for each symbol type, but the device complexity and memory requirements increase
Solution Approach 1:
The patent merges the previously separate odd and even interleaving processes into a single unified interleaver implementation. The address generator uses a single permutation circuit that handles both odd and even OFDM symbols through unified address generation logic, eliminating the need for separate interleaver instances and reducing overall device complexity while maintaining interleaving effectiveness.
Solution Approach 2:
The unified interleaver is designed to perform multiple functions - it can process both odd and even OFDM symbols using the same hardware structure. The address generator and permutation circuit are configured to adaptively generate addresses for different symbol types, making the interleaver universal and eliminating the need for mode-specific implementations.
2Ease of operation
If separate interleaver memories are allocated for odd and even symbols, then the interleaving operation is simplified, but the memory requirements and cost increase
Solution Approach 1:
The patent combines the memory resources for odd and even symbol interleaving into a single shared interleaver memory. The unified address generator produces addresses that correctly map both odd and even symbols into the same memory space, allowing the system to use one memory instance instead of two, thereby reducing memory requirements and implementation cost.
3Device complexity
If a unified interleaver is used for both odd and even symbols, then the device complexity and memory requirements are reduced, but the interleaving performance may be compromised
Solution Approach 1:
The unified interleaver incorporates local optimization by using mode-specific permutation codes for odd and even symbols. The address generator selectively applies different permutation patterns depending on the symbol type, ensuring that each symbol type receives the appropriate interleaving treatment locally, thereby maintaining high interleaving performance despite the unified structure.
Solution Approach 2:
The system maintains performance by dynamically changing parameters - specifically, the permutation code and address generation pattern are adjusted based on whether the current OFDM symbol is odd or even. This parameter adaptation allows the unified interleaver to achieve performance comparable to separate interleavers while maintaining structural simplicity.
4Reliability
If mode-specific interleavers are implemented for different DVB-T2 modes, then the interleaving is optimized for each mode, but the adaptability and implementation cost increase
Solution Approach 1:
The patent designs a universal interleaver that can operate across multiple DVB-T2 modes (2k, 4k, 8k, 16k, 32k) without requiring separate interleaver instances for each mode. The address generator and permutation circuit are configured to adapt to different mode requirements through parameter adjustment, allowing a single implementation to serve all modes effectively.
Data Source
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AI summary
A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. The data processing apparatus comprises an interleaver operable to perform an odd interleaving process which interleaves the first sets of input data symbols on to the sub-carrier signals of first OFDM symbols and an even interleaving process which interleaves the second sets of input data symbols on to the sub-carrier signals of second OFDM symbols, such that while the input data symbols from the first set are being read from locations in the interleaver memory, input data symbols from the second set can be written to the locations just read from and when input data symbols from the second set are being read from the locations in the interleaver memory, the input data symbols from a following first set can be written to the locations just read from. Furthermore, when the modulation mode is a mode which includes half or less than half a number of sub-carrier signals than a total number of sub-carriers in the OFDM symbols for carrying the input data symbols that can be accommodated by the interleaver memory, the data processing apparatus is operable to interleave the input data symbols from both first and second sets in accordance with the odd interleaving process on to the first and second OFDM symbols.