OFDM Symbol Interleaving Using LFSR Address Permutation

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Solution Overview

Problem

The existing DVB-T and DVB-H standards lack a 0.5k mode interleaver, which is necessary for more frequent channel estimation updates to accurately track time variations due to Doppler effects, and existing error correction coding schemes perform suboptimally in correlated fading environments.

Innovation Solution

A data processing apparatus with a linear feedback shift register and permutation circuit generates addresses for mapping input symbols onto OFDM sub-carrier signals, optimizing error correction by separating symbols across sub-carriers, and allowing flexible implementation across multiple modes via software changes to the generator polynomial and permutation order.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a 0.5k mode interleaver is implemented, then channel estimation accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvechannel estimation accuracyVSAvoidinterleaver complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a 0.5k mode interleaver by modifying parameters of existing interleaver structures, specifically adjusting the generator polynomial and permutation order to suit the 0.5k mode requirements. This allows achieving improved channel estimation accuracy without fundamentally redesigning the entire interleaver architecture, thus limiting the increase in device complexity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If symbols are interleaved across more sub-carriers, then error correction performance is improved, but processing time increases

Engineering Contradiction:
Improveerror correction performanceVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing the permutation order and address generation patterns for the 0.5k mode interleaver. During actual operation, the system simply retrieves these pre-computed values rather than calculating them in real-time, thus achieving widespread symbol interleaving for improved error correction without significantly increasing processing time.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If a dedicated 0.5k mode interleaver is designed, then performance in correlated fading is improved, but manufacturing cost increases

Engineering Contradiction:
Improveperformance in correlated fadingVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent achieves multi-functionality by designing the 0.5k mode interleaver using the same basic hardware architecture as existing 2k, 8k, and 4k mode interleavers. By utilizing the universal structure of linear feedback shift registers and permutation circuits with mode-specific configuration parameters, the system achieves improved performance in correlated fading for 0.5k mode without requiring entirely new manufacturing processes, thus limiting the increase in manufacturing cost.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP2204002B1Data processing apparatus and method
Publication Date: 2013.05.01 SONY GROUP CORP
  • EP2204002B1 patent drawingFigure 1
  • EP2204002B1 patent drawingFigure 2
  • EP2204002B1 patent drawingFigure 3

AI summary

A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register of R'i [7] = R'i- l[0] ? R'i-l [1] ? R'i-l [5] ? R'i-l[6] is provided with a permutation order which has been established by simulation analysis to optimise communication performance via typical radio channels, of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB- Terrestrial2 (DVB-T2).