Off-Center Metal Line Interconnects for Tight Pitch Scaling

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Solution Overview

Problem

The challenge in modern semiconductor device processing is the difficulty in forming interconnect structures with tight pitch metal lines due to limitations in extreme ultraviolet lithography and multiple-patterning techniques, which result in process variations and inaccuracies, making it hard to scale down standard cells further.

Innovation Solution

A method is developed to form interconnect structures by depositing a metal layer and capping layer, patterning the capping layer and metal layer to create off-center metal lines, forming spacer lines, and then embedding these lines in a dielectric layer, allowing for selective etching to create trenches for center and edge metal lines, which enables tight pitch metal line formation compatible with conventional self-aligned double or quadruple patterning schemes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If extreme ultraviolet lithography (EUVL) is used to form tight pitch metal lines, then the resolution and manufacturing precision should improve, but the technology is not yet mature enough to enable reliable direct printing of tight pitch metal line patterns

Engineering Contradiction:
Improvemetal line pitchVSAvoidprinting reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent divides the formation of tight pitch metal lines into multiple sequential steps: first forming off-center metal lines, then forming center and edge metal lines in separate etching steps. This segmentation allows each step to be optimized independently, achieving reliable formation of tight pitch lines that would be impossible in a single lithography step.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by first forming the off-center metal lines and their associated spacer structures before forming the center and edge metal lines. These preliminary structures serve as etch masks and spacing references for subsequent steps, enabling precise positioning without requiring direct lithographic patterning of all lines simultaneously.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If multiple-patterning techniques (SADP, SAQP) are used to form tight pitch metal lines, then the manufacturing precision may improve, but processing inaccuracies such as etch placement errors (EPE), overlay variations and critical dimension (CD) variations limit the possibility to continue the scaling

Engineering Contradiction:
Improvemetal line pitchVSAvoidetch placement accuracy
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The patent employs self-aligned processes where spacer lines are formed conformally on the off-center metal lines, automatically positioning themselves with precise spacing. The etching process uses these spacers as self-aligned masks, eliminating the need for separate alignment steps and thereby reducing overlay variations and etch placement errors that plague conventional multiple-patterning techniques.

Inventive Principle:
Principle #25Self-service

3Volume of moving object

If the track height is reduced to scale down standard cells, then the cell size decreases, but it becomes increasingly challenging to fabricate the interconnect structures with tight pitch

Engineering Contradiction:
Improvestandard cell sizeVSAvoidinterconnect fabrication
Core Design Contradiction:
Volume of moving objectVSEase of manufacture

Solution Approach 1:

The patent segments the interconnect formation into distinct phases: depositing metal and capping layers, patterning off-center lines, forming spacers, then selectively etching trenches for center and edge lines. This segmentation transforms an otherwise intractable tight-pitch fabrication problem into a sequence of manageable steps, each with relaxed process requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces spacer lines as intermediary structures that mediate between the lithographically-defined off-center metal lines and the final center/edge metal line positions. These spacers act as self-aligned etch masks, enabling precise trench formation without requiring direct lithographic definition of all metal lines, thereby facilitating tight pitch fabrication in reduced track height cells.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the reliable formation of tight pitch metal lines with well-defined horizontal electrical separation, reducing process variations and enabling the scaling of standard cells, while being compatible with existing SAQP schemes.

Implementation Method 1

depositing, on a first dielectric layer covering the active regions of the cell, a metal layer and a capping layer on the metal layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

depositing, on a first dielectric layer covering the active regions of the cell, a metal layer and a capping layer on the metal layer

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

forming spacer lines on sidewalls of the capped off-center metal lines

Methodology Applied
Scientific EffectConformal Deposition: Physical Vapour Deposition

Implementation Method 4

patterning a set of trenches in the second dielectric layer by etching the second dielectric layer selectively with respect to the capping layer and the spacer lines of the spacer-provided capped off-center metal lines

Methodology Applied
Scientific EffectSelective Etching:

Data Source

PatentUS11295977B2Standard cell device and method of forming an interconnect structure for a standard cell device
Publication Date: 2022.04.05 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • US11295977B2 patent drawing
  • US11295977B2 patent drawing
  • US11295977B2 patent drawing

AI summary

A method of forming an interconnect structure for a standard cell semiconductor device is disclosed. In one aspect, the method includes forming metal lines along respective routing tracks, wherein forming the metal lines includes depositing, on a first dielectric layer covering the active regions of the cell, a metal layer and a capping layer on the metal layer; patterning the capping layer and the metal layer to form first and second capped off-center metal lines extending along first and second off-center tracks, respectively; forming spacer lines on sidewalls of the capped off-center metal lines; and embedding the spacer-provided capped off-center metal lines in a second dielectric layer. The method further includes patterning a set of trenches in the second dielectric layer. The set of trenches includes a center trench extending along a center track between the spacer-provided capped off-center lines, and a first and a second edge trench extending along first and second edge tracks, respectively, on mutually opposite outer sides of the spacer-provided capped off-center metal lines. The method further includes forming a center metal line in the center trench, and a first and a second edge metal line in the first and second edge trenches, respectively.