Off-Center Plating Bar for Narrow Kerf Semiconductor Substrates
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Solution Overview
Problem
Conventional semiconductor substrate manufacturing processes require large kerf widths to ensure electrical isolation of plated contacts, leading to space inefficiencies and potential malfunctions due to engineering tolerances and corrosion issues with copper conductance patterns.
Innovation Solution
Positioning plating bars off-center within the kerf between adjoining package outlines, allowing for a thinner kerf width by ensuring electrical isolation without the need for wide cutting devices and maintaining the plating bar for electrical coupling, thus reducing the boundary between semiconductor package outlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electroplating processes are used with plating bars, then electrical coupling is achieved, but large kerf widths are required to ensure electrical isolation and account for engineering tolerances
Solution Approach 1:
The patent positions the plating bar off-center within the kerf, closer to one package outline than the other. This asymmetric positioning allows the kerf to be narrower because the plating bar is intentionally closer to one side, reducing the space needed on the other side while still ensuring electrical isolation of plated contacts despite engineering tolerances in the cutting process
Solution Approach 2:
The patent applies different spacing requirements to different sides of the plating bar based on local needs. By positioning the plating bar off-center, the design accommodates varying tolerance requirements on each side of the kerf, allowing for a reduced overall kerf width while maintaining reliable electrical isolation where it is most critical
2Reliability
If copper conductance patterns are used, then electrical conductivity is achieved, but corrosion resistance deteriorates due to tarnishing in the presence of moisture, air and chlorine
Solution Approach 1:
The patent uses copper as the base conductance pattern material but applies a protective plating layer (such as nickel or gold) over the copper surfaces that are exposed to the environment. This composite structure combines the high electrical conductivity of copper with the corrosion resistance of the protective plating layer, preventing tarnishing while maintaining electrical performance
Solution Approach 2:
The protective plating layer acts as an intermediary between the copper conductance pattern and the corrosive environment (moisture, air, chlorine). This intermediate layer prevents direct contact between the copper and corrosive elements, eliminating tarnishing while allowing electrical connections to function properly through the plated surfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the kerf width, increasing substrate space efficiency, enhancing semiconductor package yields, and preventing electrical shorts, while maintaining reliable electrical isolation and reducing corrosion risks.
Implementation Method 1
A current is supplied to the plating bars 116, which current travels through the plating tails 118 to the electrical terminals
Implementation Method 2
a layer of gold or other plating metal of a desired thickness may be deposited
Data Source
AI summary
A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.