Off-Center Stacked Chip Package Wire Bonding
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Solution Overview
Problem
Conventional stacked chip package structures face issues with high wire-bonding distances and accidental contacts between wires from different bonding levels, leading to potential short circuits and reduced yield in semiconductor manufacturing.
Innovation Solution
The chip package structure reconfigures the placement of bonding pads and wires, with the second chip positioned off-center relative to the first chip, allowing for shorter wire lengths and preventing crossover between first and second wires, thereby minimizing the risk of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the second chip is positioned at the central region of the first chip, then the area utilization is improved, but the wire-bonding distance increases and wire crossover occurs
Solution Approach 1:
The patent applies asymmetry by positioning the second chip at an off-center location on the first chip, specifically in the peripheral region. This asymmetric arrangement allows the bonding pads to be distributed in different regions, enabling shorter wire-bonding paths for the second chip while preventing wire crossover with the first chip's bonding wires.
2Productivity
If the wire-bonding distance is reduced, then the manufacturing efficiency is improved, but the risk of wire short circuit increases
Solution Approach 1:
The patent resolves the contradiction by utilizing spatial dimensionality - distributing bonding pads in different regions and levels. The first chip's bonding pads are in a first region, the second chip's bonding pads are in a second region, and they are arranged at different vertical levels. This multi-dimensional arrangement allows short wires without crossover, as the wires operate in separated spatial zones.
3Length of stationary object
If the bonding pads are distributed in the peripheral region, then the wire-bonding distance is reduced, but the wire crossover between different levels occurs
Solution Approach 1:
The patent applies segmentation by dividing the bonding pad distribution into distinct segments: first bonding pads in a first peripheral region for the first chip, and second bonding pads in a second peripheral region for the second chip. This segmentation ensures that wires for different chips are spatially separated, preventing crossover even when both are positioned peripherally.
Data Source
AI summary
A chip package structure including a substrate, a first chip and a second chip is provided. The first contacts and the second contacts of the substrate are respectively arranged to reside on a first side region and a second side region of the substrate. The first chip disposed on the substrate and has a plurality of first bonding pads arranged to reside on a first wire-bonding region of the first chip adjacent to the first contacts and are electrically connected to the first contacts via a plurality of first wires. The second chip is disposed on the first chip away from the symmetrical center of the first chip. The second chip has a plurality of second bonding pads arranged to reside on a second wire-bonding region of the second chip adjacent to the second contacts and are electrically connected to the second contacts via a plurality of second wires.