Off-Chip Capacitor ESD Protection for Low-Leakage IC Power Rails
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Solution Overview
Problem
Integrated circuits (ICs) with thin gate oxide regions are vulnerable to damage from electrostatic discharge (ESD) events, particularly at input terminals, and existing on-die protection methods like diodes and clamps have high leakage currents and require significant die area, which is not feasible for low-leakage current applications.
Innovation Solution
Implementing an off-chip capacitor, such as a ceramic or deep trench capacitor, coupled to the power supply rail outside the IC die to absorb ESD charge, providing effective protection without increasing die area and maintaining low leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die diodes and clamps are used for ESD protection, then ESD protection is provided, but leakage current increases and die area is consumed
Solution Approach 1:
The ESD protection function is extracted from the IC die and implemented using an external capacitor coupled to the power supply rail. This removes the harmful leakage current generation from within the die while maintaining ESD protection externally. The capacitor absorbs ESD charge without creating continuous leakage paths through the die.
Solution Approach 2:
An external capacitor is introduced as an intermediary component between the ESD event and the IC die. The capacitor couples to the power supply rail and absorbs ESD charge, acting as a mediator that protects the die without requiring internal diodes or clamps that generate leakage current.
2Reliability
If on-die ESD capacitor is used, then ESD protection is provided, but die area is exceeded
Solution Approach 1:
The ESD protection function is extracted from the IC die and implemented using an external capacitor coupled to the power supply rail. This removes the harmful leakage current generation from within the die while maintaining ESD protection externally. The capacitor absorbs ESD charge without creating continuous leakage paths through the die.
3Productivity
If thin gate oxide FETs are used, then device density is increased, but vulnerability to ESD damage increases
Solution Approach 1:
An external capacitor is placed beforehand on the power supply rail to cushion against incoming ESD events. This capacitor absorbs the ESD charge before it can reach and damage the thin gate oxide FETs, providing prior protection without requiring thicker oxide layers that would reduce device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The off-chip capacitor effectively protects the IC die and power supply rail from ESD events, reducing voltage overshoot and minimizing die area requirements while meeting low-leakage current specifications.
Implementation Method 1
an off-chip capacitor coupled to a power supply rail that provides power to the IC die. The off-chip capacitor absorbs ESD charge injected from outside the circuit system to the power supply rail
Data Source
AI summary
A circuit system includes an electronic device having a first external terminal, a second external terminal, a third external terminal, and a power supply rail coupled to the first external terminal, the second external terminal, and the third external terminal. The circuit system also includes a capacitor coupled to the power supply rail in the electronic device through the third external terminal of the electronic device. The capacitor is configured to provide voltage overshoot protection to an integrated circuit die coupled to the first external terminal during an electrostatic discharge event occurring in the power supply rail. The capacitor is external to the integrated circuit die.