Off-Chip Distributed Drain Biasing for High Power MMIC Amplifiers
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Solution Overview
Problem
High power distributed amplifier MMICs face challenges in achieving efficient DC biasing due to the limitations of on-chip bias circuitry, which can lead to reduced output power and efficiency, especially as the number of stages increases and higher DC currents are required.
Innovation Solution
An off-chip distributed drain biasing system is implemented, using parallel-connected bias chokes with series inductors and grounded capacitors to supply DC bias current to multiple FET amplifier stages, modifying the load impedance to be inductive over the entire bandwidth and matching the output impedances of the stages for improved power and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If on-chip bias circuitry is used, then the biasing is integrated and compact, but the output power and efficiency are reduced due to current capacity limitations
Solution Approach 1:
The bias circuitry is extracted from the chip and implemented off-chip using wire-wound inductors. This allows the use of higher current capacity components that are not constrained by the small chip area, thereby enabling higher output power while maintaining the integrated appearance of the MMIC.
Solution Approach 2:
Bondwires are used as intermediaries to connect the off-chip bias circuitry to the on-chip amplifier stages. The bondwires serve as current carriers that can handle the high DC bias currents required for high power operation without occupying valuable chip area.
2Device complexity
If on-chip bias circuitry is used, then the circuit is integrated, but the amplifier efficiency is reduced due to inability to provide adequate DC bias current
Solution Approach 1:
The bias circuitry is extracted from the chip to allow the use of wire-wound inductors with higher current capacity. This enables provision of adequate DC bias current to multiple amplifier stages, improving power added efficiency while maintaining a relatively simple integrated structure through off-chip implementation.
3Device complexity
If a single drain biasing method is used, then the circuit structure is simple, but the total DC bias current capability is insufficient for high power applications
Solution Approach 1:
The single drain biasing approach is segmented into multiple independent bias circuits, each serving specific amplifier stages. This segmentation allows each bias circuit to be optimized for its specific current requirements while collectively providing the high total current capability needed for high power applications.
Solution Approach 2:
Multiple bondwires serve as intermediaries to distribute DC bias current from the off-chip bias circuits to different drain terminals of the amplifier stages. This enables parallel current paths that collectively deliver high total current while maintaining a relatively simple overall structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the total DC bias current capability and enhances amplifier efficiency by matching load impedances, resulting in higher output power and improved power added efficiency across the bandwidth compared to conventional single drain biasing methods.
Implementation Method 1
Each series inductor L has sufficient impedance to block RF energy from reaching the common input over the entire bandwidth
Implementation Method 2
The capacitor provides a DC open that blocks DC current from being shunted to ground and an RF short that allows RF from the bias circuitry to flow to ground
Implementation Method 3
modifying the load impedance to be inductive over the entire bandwidth and matching the output impedances of the stages
Data Source
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AI summary
Off-chip distributed drain biasing increases output power and efficiency for high power distributed amplifier MMICs. An off-chip bias circuit has a common input for receiving DC bias current and a plurality of parallel-connected bias chokes among which the DC bias current is divided. The chokes are connected to a like plurality of drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier and add inductances to selected FET amplifier stages, typically the earlier stages, to modify the load impedance seen at the drain terminal to better match the amplifier stages to improve power and efficiency.