Off-Chip Drain Biasing for High-Power Distributed MMIC Amplifiers
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Solution Overview
Problem
High power distributed amplifier MMICs face challenges in achieving efficient DC biasing due to the limitations of on-chip DC bias circuitry, which is difficult to implement effectively at high power levels without compromising RF performance.
Innovation Solution
An off-chip distributed drain biasing system is implemented, using parallel-connected bias chokes with series inductors and grounded capacitors to supply DC bias current to multiple FET amplifier stages, modifying the load impedance to achieve better matching and increased power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-chip DC bias circuitry is used, then the bias current can be supplied to transistors, but the RF performance is compromised and the chip area is occupied (15-20%)
Solution Approach 1:
The DC bias circuitry is extracted from the chip and moved to an off-chip location. The patent implements this by removing the on-chip bias circuitry entirely and providing DC bias current through a bondwire connecting the chip to an external bias source, thereby eliminating the 15-20% chip area occupation while maintaining reliable bias current supply to all transistor stages
Solution Approach 2:
The biasing function is segmented into separate components: the DC bias current source is placed off-chip while the RF amplifier stages remain on-chip. The bondwire serves as a selective connector that separates DC bias current delivery from RF signal paths, allowing independent optimization of each function
2Object-affected harmful factors
If on-chip capacitors are used for RF blocking, then RF signals are blocked effectively, but the chip area is increased and manufacturing complexity is raised
Solution Approach 1:
The RF blocking function is extracted from on-chip capacitors and transferred to an off-chip bias circuit. The external bias circuit provides RF blocking through its design, eliminating the need for on-chip capacitors and associated manufacturing complexity while maintaining effective RF signal blocking
3Power
If wide transmission lines are used for high power applications, then large current flow is accommodated, but the chip area is increased
Solution Approach 1:
The high current carrying function is extracted from on-chip wide transmission lines and moved to an off-chip bias circuit. The external bias circuit handles the large DC bias current delivery, allowing on-chip transmission lines to be narrower and occupy less area while still accommodating the required current flow through the bondwire connection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances output power and amplifier efficiency by allowing greater DC bias current capability and minimal RF interference, improving power transfer and efficiency across the bandwidth.
Implementation Method 1
Each series inductor L has sufficient impedance to block RF energy from reaching the common input over the entire bandwidth
Implementation Method 2
The capacitor provides a DC open that blocks DC current from being shunted to ground and an RF short that allows RF from the bias circuitry to flow to ground
Implementation Method 3
Each bias choke comprises a series inductor L connected to a grounded capacitor C
Data Source
AI summary
Off-chip distributed drain biasing increases output power and efficiency for high power distributed amplifier MMICs. An off-chip bias circuit has a common input for receiving DC bias current and a plurality of parallel-connected bias chokes among which the DC bias current is divided. The chokes are connected to a like plurality of drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier and add inductances to selected FET amplifier stages, typically the earlier stages, to modify the load impedance seen at the drain terminal to better match the amplifier stages to improve power and efficiency.