Off-Chip DRAM L3 TLB for Virtual Memory Translation
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Solution Overview
Problem
Conventional processor architectures in virtualized environments face significant performance overhead due to the increased memory virtualization pressure and expensive page table walks, which are exacerbated by the need for two-dimensional page table walks and the limitations of conventional static random-access memory (SRAM) translation lookaside buffers (TLBs).
Innovation Solution
A processor architecture that incorporates a very large third-level translation lookaside buffer (TLB) implemented in off-chip or die-stacked dynamic random-access memory (DRAM), shared across processor cores, which stores recent translations of virtual memory to physical memory and reduces the number of page table walks by caching translations and using a predictor to minimize miss penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional SRAM TLBs are used, then translation speed is fast, but the TLB capacity is limited and cannot hold all translations of hot pages
Solution Approach 1:
The patent transitions from conventional on-chip SRAM TLBs to an off-chip DRAM-based L3 TLB, moving the translation buffer to a different physical dimension (off-chip memory). This dimensional change enables vastly increased capacity while accepting higher latency, and introduces a hierarchical structure with L1/L2 TLBs handling fast translations and L3 TLB handling capacity-intensive translations.
Solution Approach 2:
The patent implements a nested hierarchical TLB structure where L1 TLBs are contained within processor cores, L2 TLBs are shared among cores, and L3 TLB is implemented in off-chip DRAM. This nested arrangement allows smaller, faster TLBs to handle common cases while the larger L3 TLB provides backup capacity for hot pages.
2Reliability
If larger SRAM TLBs are used to hold more translations, then hit rate increases, but access latency increases
Solution Approach 1:
The patent segments the TLB hierarchy into multiple levels: L1 TLBs with small capacity and low latency for individual cores, L2 TLBs with moderate capacity shared among cores, and L3 TLB with large capacity in off-chip DRAM. This segmentation allows each level to optimize for its specific access pattern, maintaining high hit rates without uniformly increasing latency across all translations.
3Adaptability or versatility
If hypervisor-based virtualization is used, then system scalability improves, but memory virtualization pressure increases due to separate page tables
Solution Approach 1:
The patent implements preliminary action by pre-fetching and caching translation entries in the L3 TLB before they are actually needed. The predictor logic anticipates future translation requests and proactively loads relevant entries into the L3 TLB, reducing the need for expensive page table walks during actual translation operations.
Solution Approach 2:
The L3 TLB acts as an intermediary between the processor cores and the page tables in off-chip memory. Instead of directly accessing page tables for every translation request, the L3 TLB intercepts and resolves common translations, reducing the frequency and complexity of page table walks in virtualized environments.
Data Source
AI summary
A processor architecture utilizing a L3 translation lookaside buffer (TLB) to reduce page walks. The processor includes multiple cores, where each core includes a L1 TLB and a L2 TLB. The processor further includes a L3 TLB that is shared across the processor cores, where the L3 TLB is implemented in off-chip or die-stack dynamic random-access memory. Furthermore, the processor includes a page table connected to the L3 TLB, where the page table stores a mapping between virtual addresses and physical addresses. In such an architecture, by having the L3 TLB with a very large capacity, performance may be improved, such as execution time, by eliminating page walks, which requires multiple data accesses.