Off-Chip Memory for Distributed Tessellation Bottlenecks
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Solution Overview
Problem
Unbalanced workloads in the DirectX 11 graphics pipeline lead to bottlenecks and increased latency, as groups of patches with lower tessellation levels must wait for those with higher tessellation levels to finish processing, while other pipeline resources remain underutilized.
Innovation Solution
A method is introduced where the hull shader output data is processed in a first compute unit and stored in off-chip memory when tessellation factors exceed a threshold, allowing a second compute unit to process at least a portion of this data, thereby distributing tessellation and reducing bottlenecks by utilizing available shader resources more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If tessellation factors are increased to generate higher quality geometry, then rendering quality is improved, but processing time and pipeline latency increase significantly
Solution Approach 1:
The patent segments the tessellation processing workload by dividing patches into different processing groups based on their tessellation factors. High tessellation factor patches (e.g., factor 64 generating 8192 primitives) are processed separately from low tessellation factor patches (e.g., factor 1 generating 2 primitives). This segmentation allows the rendering pipeline to process multiple patches concurrently at different tessellation levels, preventing low-priority patches from waiting for high-priority patches to complete, thereby reducing overall pipeline latency while maintaining geometry quality.
2Manufacturing precision
If tessellation factors are increased to generate more primitives, then geometry detail is improved, but shader resource utilization becomes unbalanced and bottlenecks occur
Solution Approach 1:
The patent implements dynamic workload distribution by adjusting the processing assignment of patches based on their tessellation factors. The system dynamically assigns high tessellation factor patches to different processing units or time slots compared to low tessellation factor patches. This dynamic approach ensures that shader resources are utilized more evenly across different patch processing tasks, preventing bottlenecks caused by unbalanced workloads while maintaining the ability to generate detailed geometry where needed.
3Device complexity
If all patches are processed sequentially in a single compute unit, then processing simplicity is maintained, but pipeline efficiency decreases due to waiting time
Solution Approach 1:
The patent segments the patch processing workload across multiple compute units based on tessellation factor thresholds. Patches with tessellation factors above a threshold are routed to one compute unit while patches below the threshold are processed by another compute unit. This segmentation enables parallel processing of patches with different complexity requirements, significantly improving pipeline efficiency without requiring complex reconfiguration of the processing architecture.
Solution Approach 2:
The patent makes shader resources universal by enabling them to process multiple types of patches with different tessellation factors simultaneously. The same shader resources can handle both high tessellation factor patches (generating detailed geometry) and low tessellation factor patches (generating simplified geometry) by dynamically assigning patches to appropriate processing units. This multi-functionality improves resource utilization and pipeline efficiency without requiring separate dedicated hardware for each patch type.
Data Source
AI summary
Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (APD) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data. Once generated, hull shader output data is stored to an off-chip memory when tessellation factors associated with the shader program are greater than a configured threshold. Once stored in the off-chip memory, at least a portion of the hull shader output data is dynamically processed using a second compute unit.