Off-chip Shared Memory Arbitration via Communication Hop
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Solution Overview
Problem
Existing computing systems face challenges in efficiently managing performance among multiple integrated circuits in separate semiconductor chips, leading to increased system costs due to the need for arbitration circuitry to handle access conflicts and memory coherency.
Innovation Solution
The implementation of a computing system with at least a first and a second processing node, where these nodes coordinate their access to a shared memory without dedicated arbitration circuitry, by setting up a coordinated access schedule using a communication channel that supports point-to-point communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If arbitration circuitry is included in the semiconductor chip that includes memory devices to control access among multiple dies, then access conflicts are resolved, but system cost increases
Solution Approach 1:
The arbitration circuitry is extracted from the memory-containing semiconductor chip and relocated to a separate communication hop chip. This extraction removes the harmful complexity and cost from the memory chip while preserving the necessary arbitration functionality in a dedicated control component.
Solution Approach 2:
A separate communication hop chip is introduced as an intermediary between the processing dies and the memory devices. This intermediary chip contains the arbitration circuitry and manages access conflicts, allowing the memory chip to focus solely on storage operations without the overhead of arbitration logic.
2Quantity of substance
If multiple dies within a semiconductor chip share the capacity of memory devices, then memory capacity is utilized, but performance of individual dies is limited by arbitration
Solution Approach 1:
The system is segmented into separate functional components: processing dies in one chip, arbitration logic in a communication hop chip, and memory devices in another chip. This segmentation allows each component to operate independently at optimal performance levels without the bottlenecks of integrated arbitration.
Solution Approach 2:
The arbitration function is moved from the spatial dimension (integrated within the same chip) to a temporal dimension (separate communication hop), allowing parallel operation of arbitration and memory access without mutual interference.
3Reliability
If arbitration circuitry is included in another semiconductor chip used as a communication hop, then access among multiple dies is controlled, but system cost increases
Solution Approach 1:
The communication hop chip is designed with multi-functionality, serving both as a data transmission intermediary and as an arbitration controller. This consolidation of functions into a single chip reduces the need for additional dedicated arbitration hardware, thereby controlling system cost while maintaining access control capability.
Data Source
AI summary
An apparatus and method for efficiently managing performance among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes at least a first processing node and a second processing node. While processing tasks, the first processing node accesses a first memory and the second processing node accesses a second memory. A first communication channel transfers data between the first and second processing nodes. The first processing node accesses the second memory using a second communication channel different from the first communication channel and supports point-to-point communication. The second memory services access requests from the first and second processing nodes as the access requests are received while foregoing access conflict detection. The first processing node accesses the second memory after a particular amount of time has elapsed after reception of an indication from the second processing node specifying that a particular task has begun.