Off-Module Persistent Memory Architecture
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Solution Overview
Problem
Conventional NVDIMM devices have limited capacity due to the real estate occupied by NAND storage and memory controllers, leading to reduced DRAM capacity, high costs, and inadequate data scrambling and RAS capabilities, with data security and interleave changes posing additional challenges.
Innovation Solution
The energy-backed hybrid memory module design uses off-module storage with a supercapacitor or rechargeable battery to maintain DRAM performance while providing data persistence, allowing for shared storage across multiple modules, separate DRAM and storage elements, and supporting data scrambling and advanced RAS features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NAND storage and memory controllers are integrated into the DIMM module, then data persistence capability is improved, but the available DRAM capacity is reduced due to occupied real estate
Solution Approach 1:
The patent divides the persistent memory system into separate components: volatile DRAM modules for high-speed storage and non-volatile storage modules for data persistence. These segments are physically separated but logically connected through a memory controller that manages data transfer between them, allowing each component to optimize its function without real estate constraints
Solution Approach 2:
The patent transitions from a two-dimensional integration approach (integrating storage and controllers on the same DIMM module) to a three-dimensional architecture where DRAM modules, storage modules, and controllers are distributed across multiple dimensions in the memory subsystem, enabling scalable capacity without compromising persistence
2Reliability
If NAND storage is integrated into the DIMM module, then data persistence is achieved, but the total cost of ownership increases
Solution Approach 1:
The patent creates a universal memory architecture where a single memory controller can manage both volatile DRAM and non-volatile storage across multiple modules. This multi-functional controller reduces the need for duplicate components and enables flexible configuration, lowering overall system cost while maintaining data persistence capabilities
Solution Approach 2:
The patent enables dynamic adjustment of memory capacity and persistence parameters through software configuration rather than fixed hardware integration. This allows optimization of the DRAM-to-storage ratio based on specific application needs, reducing costs by allocating resources efficiently rather than over-provisioning all modules with expensive integrated storage
3Device complexity
If DRAM and storage are integrated in the same module, then compact design is achieved, but data scrambling and RAS capabilities are limited
Solution Approach 1:
The patent introduces a memory controller as an intermediary between DRAM modules and storage modules, enabling advanced data processing functions such as scrambling, error correction, and reliability management. This intermediary layer provides sophisticated capabilities that would be difficult to implement within integrated modules while maintaining a relatively simple overall architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively doubles the OS-visible persistent memory capacity, reduces total cost of ownership, supports data scrambling, and enhances RAS capabilities, while maintaining DRAM performance and providing secure data storage.
Implementation Method 1
The memory module includes a rechargeable battery or supercapacitor
Implementation Method 2
The memory module includes a rechargeable battery or supercapacitor
Data Source
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AI summary
Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.