Off-Package Memory Protocols for Pin-Limited High-Bandwidth DRAM
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Solution Overview
Problem
Existing data transfer technologies face challenges with excessive stress on package pin counts and signal integrity due to wide LPDDR interfaces, limiting memory bandwidth and efficiency in complex computing systems.
Innovation Solution
Implementing memory protocols over off-package interconnects using PCIe and UCIe-based links, with asymmetric lane allocation and error correction mechanisms to optimize pin count and power usage, and integrating a memory buffer chip for seamless communication between SoC and memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wide LPDDR interfaces are used to increase memory bandwidth, then data transfer speed is improved, but package pin count stress and signal integrity issues worsen
Solution Approach 1:
The patent segments the wide parallel LPDDR interface into multiple narrower serial channels that can be transmitted over off-package interconnects. Instead of using a single wide interface that stresses package pins, the data is divided into multiple serial streams that can be distributed across available package pins, reducing the burden on each individual pin while maintaining overall bandwidth.
Solution Approach 2:
The patent introduces an intermediary interface layer between the memory controller and the LPDDR memory devices. This intermediary converts the native parallel memory protocol into serial protocol suitable for off-package transmission, and then converts it back at the receiving end. This mediator resolves the incompatibility between wide parallel interfaces and narrow serial package interconnects.
2Speed
If more package pins are used to support wider interfaces, then memory bandwidth is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from a two-dimensional parallel interface approach to a time-multiplexed serial approach. Instead of expanding the interface width in the spatial dimension (which requires more pins), the patent uses the time dimension to serialize data across multiple clock cycles, achieving high bandwidth with fewer pins by utilizing time-division multiplexing.
3Device complexity
If symmetric lane allocation is used for simplicity, then device complexity is reduced, but power efficiency and performance optimization are limited
Solution Approach 1:
The patent implements asymmetric lane allocation where different numbers of serial lanes are allocated for read operations versus write operations, and for different memory channels. This asymmetry allows the system to optimize power consumption by activating only the necessary number of lanes for each operation type, rather than maintaining symmetric high-speed lanes in both directions which would consume excessive power during idle or low-bandwidth operations.
Data Source
AI summary
This disclosure describes systems, methods, and devices related to enhanced tunneled synchronization. A device may receive based on a command from a system-on-chip (SoC) device, at a memory buffer die, a plurality of command signals and associated data signals over a high-speed serial interface. The device may translate the plurality of command signals and associated data signals, at the memory buffer die, into memory protocol signals compatible with a plurality of dynamic random-access memory (DRAM) devices. The device may apply forward error correction (FEC) and cyclic redundancy check (CRC) algorithms to the command signals, data signals, and metadata at the memory buffer die. The device may transmit based on the memory protocol signals, from the memory buffer die to the DRAM devices, the corresponding data and command instructions.