Programmable Offload Region for Dynamic Task Execution

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Solution Overview

Problem

Conventional many-core and multi-core systems have a fixed topology and node configuration, leading to inefficient task execution and data transfer between computing nodes, making them cumbersome to configure and inefficient in handling computationally intensive tasks.

Innovation Solution

A programmable integrated circuit device with an offload region featuring a flexible topology that can be configured at execution time, allowing for asynchronous access to memory and dynamic reconfiguration of offload nodes to perform tasks such as processing security content, using hard intellectual property blocks for specific functions like cryptographic and mathematical operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a fixed topology and node configuration are used in many-core systems, then system stability is maintained, but task execution efficiency and data transfer performance deteriorate

Engineering Contradiction:

Improvetask execution efficiencyVSAvoidconfiguration flexibility

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic reconfiguration of the offload region topology and node configuration at execution time based on task requirements. The system transitions from a static fixed configuration to a dynamic adaptable configuration, allowing the offload region to be reconfigured for different computational tasks while maintaining system stability through controlled reconfiguration mechanisms.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent divides the programmable integrated circuit device into distinct regions: a hard processor region and an offload region. The offload region is further segmented into multiple offload nodes that can be independently configured and assigned to specific tasks. This segmentation allows flexible task distribution and parallel processing while maintaining overall system stability.

Inventive Principle:

Principle #1Segmentation

2Productivity

If physical copies of data are passed between computing nodes, then data integrity is maintained, but data transfer efficiency and system performance deteriorate

Engineering Contradiction:

Improvedata transfer efficiencyVSAvoiddata integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements a virtualization mechanism where virtual copies of data are used for transfer between computing nodes instead of physical data copies. The virtualization layer abstracts data representation, allowing efficient data sharing and transfer while maintaining data integrity through virtual reference management rather than physical duplication.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent introduces a virtualization layer as an intermediary between computing nodes that manages data transfer and sharing. This intermediary layer handles data integrity protection while enabling efficient virtual data copying and sharing, eliminating the need for inefficient physical data passage between nodes.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If security content processing is performed in software, then flexibility is maintained, but security against hacker attacks deteriorates

Engineering Contradiction:

Improvesecurity protectionVSAvoidhardware configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces software-based security content processing with hardware-based processing in the offload region. By implementing security functions in dedicated hardware blocks within the offload region, the system achieves higher security protection against hacker attacks while the hardware is configured to perform specific security-related computational tasks.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent extracts security content processing from the general-purpose hard processor region and assigns it to the specialized offload region. This separation isolates security-critical operations in a dedicated hardware domain, enhancing security protection while allowing the main processor to focus on other tasks.

Inventive Principle:

Principle #2Taking out (Extraction)

4Speed

If dedicated ASIC blocks are used for hardware specific functions, then processing speed is improved, but device complexity and configuration difficulty increase

Engineering Contradiction:

Improveprocessing speedVSAvoidconfiguration complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent creates a universal offload region that can be dynamically configured to perform multiple different functions based on task requirements. Instead of having dedicated ASIC blocks for each specific function, the offload region uses reconfigurable logic blocks that can be programmed to implement different hardware accelerators as needed, maintaining high processing speed while reducing configuration complexity through a unified interface.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9910705B1Modular offloading for computationally intensive tasks

Publication Date: 2018.03.06 ALTERA CORP

AI summary

Systems and methods are provided for configuring a programmable integrated circuit device. A hard processor region of the programmable integrated circuit device includes a processor that identifies one or more tasks for assigning to an offload region of the programmable integrated circuit. The processor in the hard processor region transmits an instruction to the offload region. The plurality of offload nodes in the offload region are configured to perform the one or more tasks.