Offload Server Automatic FPGA Processing via High-Level Synthesis
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Solution Overview
Problem
Existing techniques for offloading processing to GPUs or FPGAs face challenges such as high data exchange overhead between CPU and GPU memory, requiring skilled users for performance optimization, and often result in inefficient data transfers, making it difficult for unskilled users to improve application performance.
Innovation Solution
An offload server that analyzes application code, identifies loop statements, and uses high-level synthesis tools to specify parallel or pipeline processing on FPGAs, while reducing data transfers through explicit data transfer designations and genetic algorithms to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processing is offloaded to GPU/FPGA using CUDA or OpenCL, then computational performance is improved, but programming complexity and skill requirements increase significantly
Solution Approach 1:
The patent introduces an automatic offloading system that acts as an intermediary between the application and the accelerator. The system includes components such as an offloading instruction insertion unit that automatically inserts offloading instructions into application code, and an offloading instruction execution unit that executes these instructions. This intermediary layer abstracts the complex CUDA/OpenCL programming details from users, allowing them to achieve accelerator performance without requiring specialized programming knowledge.
2Productivity
If data is frequently transferred between CPU and GPU memory, then processing can be performed on the accelerator, but data exchange overhead increases
Solution Approach 1:
The patent implements preliminary action by pre-fetching data to the accelerator before it is needed for processing, and by pre-configuring the offloading strategy based on data access patterns. The system analyzes the application code to identify data that will be used in future computations and transfers it to the accelerator in advance, reducing the frequency and overhead of data exchanges during actual processing.
3Ease of operation
If automatic offloading is implemented without expert knowledge, then ease of operation improves, but optimization performance may deteriorate
Solution Approach 1:
The patent incorporates feedback mechanisms where the system monitors the performance of offloaded operations and uses this information to dynamically adjust offloading strategies. The feedback loop includes performance measurement units that collect data on execution time, resource utilization, and data transfer overhead, which are then used by the optimization unit to refine offloading decisions and improve performance over time without requiring expert intervention.
Data Source
AI summary
An offload server includes a PLD processing designation section configured to specify parallel processing or pipeline processing on a PLD by using a high-level synthesis tool including OpenCL, and a PLD processing pattern generation section configured to exclude, from loop statements to be offloaded, any iteration statement at which a compilation error occurs and to generate PLD processing patterns each of which specifies whether to perform PLD processing for each of the iteration statements at which no compilation error occurs.