Offloading Server Automates GPU Code Generation

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Solution Overview

Problem

Existing methods for offloading processing to GPUs are inefficient for unskilled users, requiring technical expertise and trial-and-error approaches to achieve good performance, often resulting in suboptimal CPU-GPU data exchange overhead and limited acceleration of applications.

Innovation Solution

An offloading server that analyzes application code, identifies loop statements, and uses explicit directives to optimize data transfers and parallel processing, employing a genetic algorithm to automatically select the most effective parallel processing patterns and reduce data transfer inefficiencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If manual programming and settings according to hardware (CUDA, OpenCL) are required to utilize GPU or FPGA, then processing performance can be improved, but the technical hurdle and complexity increase significantly

Engineering Contradiction:
Improveprocessing performanceVSAvoidtechnical knowledge requirement
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system performs self-service by automatically analyzing application source code, identifying parallelizable processing sections, and generating optimized accelerator code without requiring user intervention. The offloading server autonomously completes tasks that would otherwise require expert programming knowledge in CUDA or OpenCL.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The offloading server acts as an intermediary between the application developer and the accelerator hardware. It translates high-level application code into optimized accelerator code, shielding users from the complexity of direct hardware programming while enabling efficient GPU or FPGA utilization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If trial-and-error approaches are used to achieve good performance in CPU-GPU data exchange, then processing performance can be improved, but time consumption and complexity increase

Engineering Contradiction:
Improveprocessing performanceVSAvoidoptimization time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system performs preliminary analysis of the application source code to identify optimal data transfer points and parallelizable sections before actual execution. By pre-determining the best optimization strategy through static analysis, it eliminates the need for time-consuming trial-and-error runtime adjustments.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system incorporates performance measurement functionality that provides feedback on actual accelerator performance, allowing automatic adjustment and optimization of data transfer strategies based on measured results rather than relying on manual trial-and-error approaches.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If automatic offloading of application processing to accelerator is implemented, then ease of use improves, but processing performance may be reduced without proper optimization

Engineering Contradiction:
Improveease of useVSAvoidprocessing performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The system segments the application source code to identify specific parallelizable processing sections that are suitable for accelerator offloading. By carefully selecting and separating only the appropriate portions for acceleration while keeping other sections on the CPU, it maintains ease of automatic offloading while ensuring optimal processing performance.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11403083B2Offloading server and offloading program
Publication Date: 2022.08.02 NIPPON TELEGRAPH & TELEPHONE CORP
  • US11403083B2 patent drawing
  • US11403083B2 patent drawing
  • US11403083B2 patent drawing

AI summary

An offloading server includes: a data transfer designation section configured to analyze reference relationships of variables used in loop statements in an application and designate, for data that can be transferred outside a loop, a data transfer using an explicit directive that explicitly specifies a data transfer outside the loop; a parallel processing designation section configured to identify loop statements in the application and specify a directive specifying application of parallel processing by an accelerator and perform compilation for each of the loop statements; and a parallel processing pattern creation section configured to exclude loop statements causing a compilation error from loop statements to be offloaded and create a plurality of parallel processing patterns each of which specifies whether to perform parallel processing for each of the loop statements not causing a compilation error.