Offset 3D Multi-Chip Package for Higher Memory Density
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Solution Overview
Problem
Conventional multi-chip modules face challenges in incorporating additional memory chips without increasing the physical footprint of the interposer and package substrate, which often requires redesigning the socket and circuit boards.
Innovation Solution
The solution involves stacking smaller chips over a larger processor or integrated circuit, with at least partial lateral overlap, using a reconstituted package that maintains the original footprint, incorporating additional memory devices while preserving existing socket sizes and designs, utilizing a silicon interposer with through-substrate vias and dielectric layers for electrical connectivity and stress relief.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional memory chips are mounted side-by-side on the interposer, then the memory capacity increases, but the physical footprint of the interposer and package substrate increases
Solution Approach 1:
The patent transitions from a 2D side-by-side chip arrangement to a 3D stacked configuration where memory chips are positioned above and below the processor chip. This vertical stacking enables additional memory capacity while maintaining the same interposer footprint, directly resolving the contradiction between increasing memory capacity and minimizing physical area.
Solution Approach 2:
The patent implements a nested structure where memory chips are stacked vertically around the processor chip in multiple layers. The first and second memory chips are positioned above the processor chip, while the third and fourth memory chips are positioned below it, creating a compact nested arrangement that maximizes memory density within the constrained footprint.
2Quantity of substance
If the interposer size is increased to accommodate more chips, then more memory devices can be integrated, but the socket and circuit boards require redesign
Solution Approach 1:
By stacking memory chips vertically in three dimensions rather than expanding horizontally in two dimensions, the patent integrates more memory devices without increasing the interposer's planar footprint. This maintains compatibility with existing socket and circuit board designs, avoiding the complexity of redesign.
3Quantity of substance
If memory chips are arranged around the periphery of the processor chip, then connectivity is achieved, but the density of memory integration is limited
Solution Approach 1:
The patent extends connectivity into the vertical dimension by implementing through-silicon vias (TSVs) that penetrate the processor chip to electrically connect memory chips positioned above and below the processor. This enables high-density memory integration in 3D space while maintaining electrical connectivity through the vertical stacking arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the integration of more memory devices within the same physical footprint, enhancing module performance without the need for socket redesign, while maintaining compatibility with existing circuit boards and socket sizes.
Implementation Method 1
The semiconductor chips include respective underfill material layers to lessen the effects of differential thermal expansion due to differences in the coefficients of thermal expansion of the chips, the interposer and the solder joints.
Data Source
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AI summary
Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package (115) that includes an interposer (125) that has a first side and a second and opposite side and a metallization stack (145) on the first side, a first semiconductor chip (25) on the metallization stack and at least partially encased by a dielectric layer (165) on the metallization stack, and plural semiconductor chips (40, 45) positioned over and at least partially laterally overlapping the first semiconductor chip.