Offset-Adjustable ADC Comparators Without a Resistor Ladder
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) face challenges in power consumption and area efficiency, particularly in high-resolution applications, due to static current through resistor ladders and interleaved mismatches in time-interleaved SAR ADCs, which limit their performance and speed.
Innovation Solution
The proposed ADC employs offset-adjustable comparators with embedded constant and adaptive offsets, eliminating the need for a resistor ladder and enabling fast switching of embedded reference voltages, reducing power consumption and area requirements by using a track and hold circuit, clock generator, coarse and fine ADC circuits, and an encoder to generate a digital signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a resistor ladder is used to generate reference voltages in flash ADC, then high-speed conversion is achieved, but power consumption increases due to static current and area increases exponentially with resolution
Solution Approach 1:
The patent extracts and eliminates the resistor ladder component from the ADC architecture. By using offset-adjustable comparators with embedded reference voltages instead of a resistor ladder, the design removes the source of static current consumption while maintaining high-speed conversion capability through parallel comparator operation
Solution Approach 2:
The patent changes the operational parameters of comparators by introducing offset-adjustable capabilities with embedded reference voltages. This allows the comparators to operate without requiring continuous bias current from a resistor ladder, thereby reducing power consumption while maintaining the speed performance through optimized comparator circuit design
2Speed
If a resistor ladder is used to generate reference voltages in flash ADC, then high-speed conversion is achieved, but area increases exponentially with resolution
Solution Approach 1:
The patent extracts and eliminates the resistor ladder component from the ADC architecture. By using offset-adjustable comparators with embedded reference voltages instead of a resistor ladder, the design removes the large area requirement while maintaining high-speed conversion capability through parallel comparator operation
Solution Approach 2:
The offset-adjustable comparators serve multiple functions: they provide comparison operation, generate reference voltages through embedded structures, and eliminate the need for external resistor ladders. This multi-functionality reduces the overall circuit area while maintaining high-speed performance
3Use of energy by moving object
If time-interleaved SAR ADC is used to achieve high speed conversion with good power efficiency, then power efficiency is improved, but performance decreases due to interleaved mismatches among channels
Solution Approach 1:
The patent introduces offset-adjustable comparators that can be calibrated to compensate for mismatches. By providing feedback mechanisms through the offset adjustment capability, the system can correct for channel mismatches in time-interleaved architectures, thereby maintaining both power efficiency and measurement precision
4Use of energy by moving object
If subranging ADC with multiplexing circuit and resistor ladder is used, then trade-off between flash ADC and time-interleave SAR ADC is achieved, but settling time of reference-voltage switching limits operation speed
Solution Approach 1:
The patent extracts and eliminates the resistor ladder and multiplexing circuit from the subranging ADC architecture. By using offset-adjustable comparators with embedded reference voltages, the design removes the switching bottleneck that limited operation speed, enabling faster reference voltage switching without the need for large resistor ladders
Solution Approach 2:
The patent introduces dynamic offset adjustment capability in the comparators, allowing the reference voltages to be switched rapidly without the settling time limitations of traditional resistor ladder-based systems. This dynamic adjustment enables faster operation while maintaining power efficiency
Data Source
AI summary
An analog to digital converter includes a coarse ADC circuit composed of L offset-adjustable comparators and a fine ADC circuit composed of M offset-adjustable comparators. Each offset-adjustable comparator in the coarse ADC circuit has a constant embedded offset. Each offset-adjustable comparator in the fine ADC circuit has an adaptive embedded offset digitally determined by outputs of the coarse ADC circuit. With the constant and adaptive embedded offsets, the analog to digital converter requires no resistor ladder. Therefore, power consumption and area of the analog to digital converter is reduced, and faster conversion speed is achieved.