Offset-Bias Level Shifter for Low-Leakage Multi-Voltage Circuits
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Solution Overview
Problem
Existing level shifters in high-voltage electronic circuits suffer from high leakage currents and poor linearity due to variations in input signal magnitude, especially when transitioning between low and high voltage domains.
Innovation Solution
An electronic circuit with a voltage-offset circuit, push-pull circuit, bias circuit, and high-voltage stand-off circuit that generates a stable offset-bias voltage, using diode-connected p-FETs and variable current sources to stabilize the voltage difference between high and low voltage domains, reducing leakage and improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifters are used to shift voltage levels between low and high voltage domains, then voltage level shifting is achieved, but high leakage currents are generated
Solution Approach 1:
The level shifter is divided into multiple independent circuits: a first circuit generates the offset-bias voltage using diode-connected p-FETs, a second circuit provides bias current, and a third circuit performs the actual level shifting. This segmentation allows each circuit to be optimized for its specific function, reducing overall leakage current while maintaining voltage shifting capability.
Solution Approach 2:
An offset-bias voltage is introduced as an intermediary element between the high voltage rail and the output. This offset-bias voltage is generated through a dedicated voltage-offset circuit using diode-connected p-FETs, which provides a stable reference that reduces leakage currents in the main level shifting path.
2Reliability
If existing level shifters are used with voltage swing tied to input signal magnitude, then voltage level shifting is achieved, but poor linearity is exhibited when input signal magnitude varies
Solution Approach 1:
The invention changes the parameter of voltage reference by using an offset-bias voltage that is independent of the input signal magnitude. The voltage-offset circuit generates this offset-bias voltage through diode-connected p-FETs, ensuring that the voltage swing in the high voltage domain remains consistent and linear regardless of variations in the input signal magnitude.
3Power
If high-voltage circuits operate at high voltages (e.g., 24V, 48V, 100V, 200V), then power delivery capability is improved, but transistor operation becomes limited due to low voltage tolerance (e.g., 5.5V or less)
Solution Approach 1:
The system is segmented into a low-voltage control domain and a high-voltage power domain. The low-voltage digital control circuits operate safely within their voltage tolerance (e.g., 5.5V), while the high-voltage circuits (operating at 24V, 48V, 100V, or 200V) are isolated by the level shifter. This allows each domain to operate independently at its optimal voltage level.
Solution Approach 2:
The level shifter acts as an intermediary interface between the low-voltage control domain and the high-voltage power domain. It translates control signals from the low-voltage domain to the high-voltage domain, enabling high-voltage circuits to be controlled by low-voltage digital logic without exposing the control circuits to dangerous high voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit achieves a stable output voltage difference in the high voltage domain, insensitive to process, voltage, and temperature variations, with low power consumption and high frequency operation, while minimizing leakage currents.
Implementation Method 1
a voltage-drop circuit (512) comprising a series arrangement of a set of M−1 diode-connected p-FETs (P1, P3) each having a gate-source voltage Vgs, connected between the high-voltage-supply terminal and a first node (528) of the push-pull circuit to provide a voltage (M−1). Vgs therebetween
Implementation Method 2
at least one, N, n-FET connected between the high-voltage-supply terminal and the bias output terminal and having a threshold voltage Vt, and arranged to provide a voltage difference Vgs+N·(Vt) between the first node and the offset-bias output terminal
Data Source
AI summary
An electronic circuit that switchably generates an offset-bias output at a offset-bias voltage in response to at least an enable signal at a low voltage relative to the offset-bias voltage is provided. The electronic circuit includes a reference input terminal, configured to be connected to a reference voltage; a low-voltage-input terminal, configured to receive the enable signal at a first voltage; a high-voltage-supply terminal, configured to receive power at a second voltage; an offset-bias output terminal, configured to output the offset-bias output, the offset-bias voltage being less than the second voltage; a voltage-offset circuit configured to generate the offset-bias voltage from the second voltage; a bias circuit configured to switchably provide a bias current to the voltage-offset circuit; and a high-voltage stand-off circuit, connected between the bias circuit and the voltage-offset circuit and configured to withstand a voltage difference between the second voltage and the reference voltage.