Offset Bit Line Non-Volatile Memory Element
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Solution Overview
Problem
Existing non-volatile memory elements using phase change materials face challenges in minimizing heat radiation to bit lines during data writing, particularly when miniaturized, due to the need for through-holes and interlayer insulation films, which increase manufacturing complexity and costs.
Innovation Solution
A non-volatile memory element design where the bit line is offset to the recording layer, eliminating the need for an interlayer insulation film between the upper electrode and the bit line, thereby reducing contact areas and heat radiation, and a manufacturing method involving steps to form a laminate structure without through-holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If an interlayer insulation film is arranged between the upper electrode and the bit line to reduce heat radiation, then heat efficiency is improved, but device complexity and manufacturing difficulty increase due to the need for through-holes and embedded conductive materials
Solution Approach 1:
The patent extracts and eliminates the interlayer insulation film from the structure, replacing it with a direct contact configuration where the bit line is offset to the recording layer. This removes the complex through-hole formation and conductive material embedding processes while maintaining heat radiation suppression through the offset geometry.
Solution Approach 2:
The patent introduces an offset configuration in the planar dimension, positioning the bit line laterally offset to the recording layer rather than using a vertical through-hole structure. This dimensional change eliminates the need for complex vertical interconnections while maintaining thermal isolation.
2Productivity
If the non-volatile memory element is miniaturized to increase storage capacity, then productivity is improved, but manufacturing precision requirements worsen due to difficulty in forming through-holes and embedding conductive materials
Solution Approach 1:
The patent removes the through-hole formation step from the manufacturing process by eliminating the interlayer insulation film structure. This extraction of the problematic feature enables miniaturization without the escalating precision requirements that would otherwise be needed for forming and filling increasingly small through-holes.
Solution Approach 2:
The patent segments the bit line and recording layer into offset positions, creating distinct functional zones that eliminate the need for precise through-hole alignment. This segmentation allows independent optimization of each component's dimensions without the coupled precision constraints of through-hole formation.
3Reliability
If through-holes are formed and conductive materials are embedded to connect upper electrode and bit line, then electrical connectivity is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent merges the bit line and upper electrode into a direct offset configuration, eliminating the need for separate through-hole formation and conductive material embedding steps. This merging of functions maintains electrical connectivity through the offset geometry while reducing manufacturing process complexity and cost.
Solution Approach 2:
The patent extracts and eliminates the interlayer insulation film and associated through-hole formation processes, replacing them with a simpler direct contact structure. This removal of unnecessary components reduces manufacturing steps, materials, and costs while maintaining reliable electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses heat radiation to the bit line while maintaining connectivity between the upper electrode and bit line, enhancing heat efficiency and reducing manufacturing complexity, even in miniaturized forms.
Implementation Method 1
the storage of data is based on the phase state of phase change material contained in the recording layer. Specifically, there is a big difference between the electrical resistivity of the material in the crystalline state and the electrical resistivity in the amorphous state
Implementation Method 2
This phase change is effected by the phase change material being heated when a write current is applied
Implementation Method 3
there is known a structure in which the top surface of a recording layer is covered with an upper electrode having low thermal conductivity, thereby reducing heat radiation to a bit line having a large thermal capacity and high thermal conductivity
Data Source
AI summary
A non-volatile memory element includes a lower electrode, an upper electrode, a recording layer arranged between the lower electrode and the upper electrode and containing a phase change material, and a bit line directly arranged on the upper electrode. The bit line is formed to be offset to the recording layer. With this arrangement, a contact area between the recording layer and the upper electrode and a contact area between the upper electrode and the bit line can be reduced without providing an interlayer insulation film between the upper electrode and the bit line. Thus, heat radiation to the bit line can be suppressed while the upper electrode and the bit line are connected without using a through-hole.