Offset Bit Line Regions in 4T2C NVM Cells
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Solution Overview
Problem
Multi-time programmable (MTP) cells in non-volatile memory (NVM) face reliability issues due to damage to the gate dielectric structure during programming operations, leading to device failure and inaccurate read operations, especially in high-voltage applications with smaller transistors.
Innovation Solution
A four-transistor-two-capacitor (4T2C) configuration memory cell design is introduced, where the bit line write and read active regions are laterally offset, isolating Fowler-Nordheim tunneling during programming from the bit line read active region to prevent damage to the gate dielectric structure, thereby increasing the number of programmable operations and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional MTP cell design is used, then integration with HV CMOS technology is achieved, but gate dielectric structure damage occurs during programming operations
Solution Approach 1:
The patent segments the bit line active region into two separate regions: a first bit line active region for write operations and a second bit line active region for read operations. This segmentation isolates the Fowler-Nordheim tunneling process to only the first region during programming, preventing damage to the gate dielectric structure overlying the second region while maintaining integration with HV CMOS technology.
2Duration of action of moving object
If Fowler-Nordheim tunneling is used for programming, then multi-time programmability is achieved, but gate dielectric structure damage occurs
Solution Approach 1:
The patent applies local quality by creating different functional zones within the same memory cell structure. The first bit line active region is designed to withstand repeated Fowler-Nordheim tunneling stress for multi-time programmability, while the second bit line active region maintains high-quality gate dielectric structure for accurate read operations. This localized differentiation allows the cell to achieve both multi-time programmability and high reliability.
3Device complexity
If bit line active region is shared for read and write operations, then device complexity is reduced, but read accuracy deteriorates due to dielectric damage
Solution Approach 1:
The patent divides the bit line active region into separate first and second regions for write and read operations respectively. This segmentation prevents the gate dielectric structure from suffering cumulative damage during programming operations, thereby maintaining read accuracy. The separate regions are laterally offset from each other, ensuring that Fowler-Nordheim tunneling during write operations does not affect the quality of the gate dielectric overlying the read region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 4T2C configuration significantly enhances the endurance and reliability of the memory cell by reducing damage to the gate dielectric structure, allowing for more program and erase operations without inaccurate read operations, even in applications with smaller transistors.
Implementation Method 1
isolating Fowler-Nordheim tunneling during programming from the bit line read active region
Data Source
AI summary
A memory cell may include first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.