Offset Bonding Pad Layout for Semiconductor Wafer Reliability
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Solution Overview
Problem
The existing semiconductor devices using wafer bonding techniques face challenges with pad bonding failures and size constraints, where increasing pad size reduces open failures but increases short failures, and reducing pad size minimizes short failures but may lead to larger device sizes, hindering miniaturization.
Innovation Solution
The semiconductor device incorporates a unique layout where first and second bonding pads on the peripheral and cell wafers are offset in the row direction, and the shape of the pads is optimized to increase the interval between adjacent pads without changing their size, reducing the likelihood of pad bonding failures while maintaining a compact device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pad size is increased to reduce open failures, then bonding reliability improves, but device size increases
Solution Approach 1:
The bonding pads are arranged in an asymmetric offset pattern where first bonding pads and second bonding pads are positioned in different rows and offset in the row direction. This asymmetric layout increases the interval between adjacent pads without requiring larger pad dimensions, thereby maintaining bonding reliability while preventing device size increase.
2Area of stationary object
If pad size is reduced to minimize short failures, then device size decreases, but bonding reliability deteriorates
Solution Approach 1:
The pad layout utilizes the row direction offset to create additional spatial separation between bonding pads. By arranging first and second bonding pads in different rows with offset positioning, the invention effectively uses the row direction dimension to increase intervals between pads, reducing short failures without requiring larger pad sizes.
3Reliability
If pad interval is increased to reduce short failures, then bonding reliability improves, but device size increases
Solution Approach 1:
The asymmetric offset arrangement of bonding pads in different rows achieves increased interval between pads without requiring uniform expansion of the pad array. This selective spacing through asymmetric positioning reduces short failures while maintaining compact device dimensions.
Data Source
AI summary
A semiconductor device includes a first wafer including a row decoder region in which a plurality of pass transistors are arranged in a row direction and a column direction; a plurality of first bonding pads, respectively coupled to the plurality of pass transistors that are disposed in a plurality of rows on one surface of the first wafer in the row decoder region; and a plurality of second bonding pads disposed on the one surface of the first wafer in the row decoder region, wherein the plurality of second bonding pads are disposed in a different row from the plurality of first bonding pads and are offset in the row direction with respect to the plurality of first bonding pads.