Offset Channel MIS Transistor for Chip Area Reduction
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Solution Overview
Problem
The miniaturization of semiconductor devices is hindered by the dimensional difference between core and I/O transistors, leading to reduced scaling effects and increased chip area, as the core transistor's circuit area reduction results in increased circuit occupancy by the I/O transistor, slowing down overall chip miniaturization.
Innovation Solution
A semiconductor device is designed with a first MIS transistor driven at a low source voltage and a second MIS transistor driven at a high source voltage, featuring a channel region offset relative to the impurity diffusion region, which reduces parasitic resistance and suppresses excessive ON current, allowing for a reduced gate length and minimized chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate length of the second MIS transistor is reduced to minimize chip area, then the circuit area is reduced, but excessive ON current occurs affecting reliability
Solution Approach 1:
The patent applies local quality by creating an offset structure specifically in the second MIS transistor where the channel region is positioned away from the impurity diffusion region. This local structural modification increases parasitic resistance only in the high-voltage transistor, suppressing excessive ON current without affecting the first transistor's performance, thus resolving the contradiction between miniaturization and reliability.
2Reliability
If the channel region is offset relative to the impurity diffusion region in the second MIS transistor, then parasitic resistance increases suppressing excessive ON current, but this structural complexity increases device complexity
Solution Approach 1:
The patent uses segmentation by differentiating the structure of the first and second MIS transistors. The second transistor is segmented with an offset channel region relative to the impurity diffusion region, while the first transistor maintains a conventional aligned structure. This selective segmentation achieves the desired parasitic resistance increase only where needed, balancing reliability improvement with acceptable device complexity.
3Speed
If the gate length is reduced to increase processing speed, then the processing speed improves, but excessive ON current and off-leak current occur
Solution Approach 1:
The patent applies parameter changes by modifying the spatial relationship between the channel region and impurity diffusion region through offsetting. This structural parameter change increases parasitic resistance, which compensates for the reduced gate length effects, thereby suppressing excessive ON current and off-leak current while maintaining high processing speed achieved through gate length reduction.
Data Source
AI summary
In a semiconductor device including a core transistor and an I/O transistor on the same semiconductor substrate, the core transistor includes a gate insulating film, a gate electrode, sidewalls, extension diffusion layers, and source/drain diffusion layers. The I/O transistor includes a gate insulating film, a gate electrode, sidewalls, and source/drain diffusion layers. In the I/O transistor, the source/drain diffusion region is offset relative to a channel region located beneath the gate insulating film in regions below the sidewalls.