Offset-Stacked Semiconductor Package for Edge Peeling Resistance

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Solution Overview

Problem

In multi-chip semiconductor packages, edge peeling-off failures occur due to differences in hygroscopic expansion at triple points where different materials meet, leading to reliability issues.

Innovation Solution

A semiconductor package design featuring a stress relieving adhesive layer that covers the side surfaces of the first semiconductor chip under the overhang region of the second chip, preventing direct contact with the molding member's EMC material, and a method of manufacturing involving a die attach process with offset-alignment of chips to expose chip pads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If chips are stacked in zigzag or cascade arrangement with overhang regions, then chip stacking is achieved, but edge peeling-off failure occurs due to hygroscopic expansion differences at triple points

Engineering Contradiction:
Improvechip stacking capabilityVSAvoidedge peeling-off resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A stress relieving adhesive layer is introduced as an intermediary material between the lower chip and the upper chip's overhang region. This adhesive layer specifically addresses the triple point where the lower chip, upper chip, and molding compound meet, preventing edge peeling-off by compensating for hygroscopic expansion differences. The adhesive layer has thickness of 1-10 μm and is positioned to cover the side surface of the lower chip under the overhang region, thereby eliminating the harmful stress concentration at the triple point while maintaining the zigzag or cascade stacking arrangement.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If stress relieving adhesive layer is applied to cover side surfaces under overhang region, then edge peeling-off is prevented, but manufacturing complexity increases

Engineering Contradiction:
Improveedge peeling-off resistanceVSAvoidadhesive layer application process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The stress relieving adhesive layer is applied locally only where needed - specifically on the side surface of the lower chip under the overhang region where the triple point exists. Rather than applying adhesive uniformly across the entire chip surface, the adhesive is positioned precisely at the critical stress concentration zone. This localized application approach maintains manufacturing simplicity while effectively preventing edge peeling-off failures at the critical triple point location.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents edge peeling-off failures by managing stress concentrations and hygroscopic expansion differences, enhancing the mechanical reliability of the semiconductor package.

Implementation Method 1

edge peeling-off failure due to a difference in hygroscopic expansion may occur in the triple point

Methodology Applied
Scientific EffectHygroscopic expansion:

Data Source

PatentUS20240379620A1Semiconductor package and method of manufacturing the semiconductor package
Publication Date: 2024.11.14 SAMSUNG ELECTRONICS CO LTD
  • US20240379620A1 patent drawing
  • US20240379620A1 patent drawing
  • US20240379620A1 patent drawing

AI summary

A semiconductor package includes a package substrate. A first semiconductor chip is arranged on the package substrate. A second semiconductor chip is disposed on the first semiconductor chip by an adhesive film. The second semiconductor chip is offset-aligned with the first semiconductor chip in a horizontal direction. A stress relieving adhesive layer is disposed on the first semiconductor chip and covers an upper surface of the first semiconductor chip. The stress relieving adhesive layer extends vertically downward from the upper surface to cover a side surface of the first semiconductor chip under an overhang region of the second semiconductor chip. A molding member covers the first semiconductor chip and the second the semiconductor chip on the package substrate.