Offset Stacked Semiconductor Package for Dense Chip Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for smaller, more functional electronic devices requires advanced semiconductor packaging solutions that efficiently integrate multiple semiconductor chips while maintaining electrical connectivity and structural integrity.
Innovation Solution
A semiconductor package design featuring a redistribution structure with insulating layers and conductive patterns, along with vertical connection wires and conductive pillars, allows for the stacking and electrical connection of multiple semiconductor chips, including a first chip with a through-electrode and a second chip offset from the first, using inter-chip connection bumps and conductive pillars, all encapsulated within a molding layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase integration density, then the functional capacity increases, but the manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
The patent divides the semiconductor package into multiple independent chips (first semiconductor chip, second semiconductor chip) that can be manufactured separately and then stacked. Each chip has its own substrate and connection structures, allowing independent fabrication and testing before assembly, thereby reducing overall manufacturing complexity while maintaining high integration density
Solution Approach 2:
The patent transitions from planar side-by-side chip arrangement to vertical stacking configuration. By utilizing the vertical dimension (Z-axis) instead of only horizontal space (X-Y plane), the package achieves higher integration density without proportionally increasing manufacturing complexity, as the stacking process follows standardized vertical alignment procedures
2Volume of moving object
If chips are stacked vertically to reduce package size, then the volume efficiency improves, but the alignment precision and connection reliability requirements worsen
Solution Approach 1:
The patent implements a nested structure where the second semiconductor chip is positioned on top of the first semiconductor chip, with connection bumps and conductive pillars providing mechanical interlocking. This nesting approach ensures precise alignment through physical guides and registration features, reducing alignment precision requirements while achieving compact vertical stacking
Solution Approach 2:
The patent introduces intermediary connection structures (connection bumps, conductive pillars, and molding layer) between the stacked chips. These intermediaries serve as alignment references and mechanical connectors, facilitating precise positioning and reliable electrical connections while maintaining compact package dimensions
3Reliability
If complex interconnection structures are used to achieve electrical connectivity between stacked chips, then the connectivity reliability improves, but the manufacturing process complexity increases
Solution Approach 1:
The patent combines multiple connection functions into integrated structures. The conductive pillars serve both as mechanical support elements and electrical interconnects, while the molding layer simultaneously provides encapsulation, mechanical support, and electrical insulation. This merging reduces the number of separate manufacturing steps while ensuring reliable electrical connectivity between stacked chips
Solution Approach 2:
The patent designs multi-functional components that perform multiple roles. For example, the connection bumps provide both mechanical attachment and electrical connection functions, and the redistribution structures serve both signal routing and mechanical alignment purposes. This multi-functionality simplifies the overall manufacturing process by reducing the number of specialized steps required
4Reliability
If redistribution structures with multiple insulating layers are used to route signals, then the signal transmission quality improves, but the manufacturing steps and time increase
Solution Approach 1:
The patent performs preliminary formation of redistribution patterns and insulating layers during the chip fabrication process itself, before the stacking assembly. This preliminary action allows the redistribution structures to be pre-tested and pre-aligned, reducing the time required for final package assembly while ensuring high signal transmission quality through controlled impedance and routing
Data Source
AI summary
A semiconductor package includes a first redistribution structure, a first semiconductor chip on the first redistribution structure and including a first through-electrode, a second semiconductor chip on the first semiconductor chip and including a central portion vertically overlapping the first semiconductor chip and an outer portion horizontally offset from a sidewall of the first semiconductor chip, a molding layer in contact with the first redistribution structure, the first semiconductor chip, and the second semiconductor chip, a second redistribution structure on the second semiconductor chip and the molding layer, a first vertical connection wire extending through the molding layer and extending from the first redistribution structure to the second redistribution structure, and a second vertical connection wire extending through the molding layer and extending from the first redistribution structure to the outer portion of the second semiconductor chip.