Offset Chip Stack Layout for Compact High-Frequency Packaging
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Solution Overview
Problem
There is a need for compact-sized semiconductor packages with improved electrical properties, particularly for high-frequency operations, to meet the demands of portable electronic devices.
Innovation Solution
A semiconductor package design featuring a first chip stack with offset-stacked semiconductor chips, a spacer, and a second chip stack, where connection wires are spaced apart from adhesion layers, allowing for a miniaturized and structurally rigid package with enhanced electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple semiconductor chips are stacked vertically to reduce package area, then the area of the semiconductor package is reduced, but the electrical properties deteriorate due to interference between connection wires and adhesion layers
Solution Approach 1:
The patent transitions from a conventional vertical stacking approach to an offset stacking arrangement where chips are positioned at different horizontal levels. This dimensional reconfiguration allows connection wires to be routed along the side surfaces of chips rather than through the vertical stack, eliminating interference with adhesion layers while maintaining compact footprint.
Solution Approach 2:
The patent divides the connection path into separate segments: connection pads on chip surfaces, connection wires routed along side surfaces, and adhesion layers on bottom surfaces. This segmentation isolates the electrical connection function from the mechanical bonding function, allowing both to operate independently without interference.
2Strength
If adhesion layers are made thicker to ensure structural integrity, then the strength of the package increases, but the electrical properties worsen due to increased interference with connection wires
Solution Approach 1:
The patent separates the structural bonding function (adhesion layers on bottom surfaces) from the electrical connection function (wires on side surfaces). This allows adhesion layers to be optimized for mechanical strength without compromising electrical performance, as they no longer occupy the same spatial domain as the connection wires.
Solution Approach 2:
The patent applies different functional qualities to different locations: adhesion layers are concentrated at the bottom surfaces for structural support, while connection wires are positioned along side surfaces for electrical connectivity. This local differentiation allows each component to be optimized for its specific function without interfering with the other.
3Use of energy by moving object
If connection wires are routed closer to adhesion layers to reduce wire length, then the use of energy decreases, but the electrical properties worsen due to interference and inductance effects
Solution Approach 1:
The patent moves the connection wire routing from the vertical dimension (through the stack) to the horizontal dimension (along side surfaces). This dimensional shift eliminates the trade-off between wire length and interference, as wires can be routed efficiently along the offset chip surfaces without crossing adhesion layer paths.
Solution Approach 2:
The offset chip structure itself acts as an intermediary that provides a dedicated pathway for connection wires along its side surfaces. This intermediary structure separates the wire routing function from the adhesion layer function, allowing both to coexist without interference while maintaining efficient electrical connectivity.
Data Source
AI summary
Disclosed is a semiconductor package comprising a first chip stack including on a substrate a plurality of first semiconductor chips in an offset stack structure and stacked to expose a connection region at a top surface of each of the first semiconductor chips, a second semiconductor chip on the substrate and horizontally spaced apart from the first chip stack, a spacer on the second semiconductor chip, and a second chip stack including third semiconductor chips in an offset stack structure on the first chip stack and the spacer. Each of the first semiconductor chips includes a first chip pad on the connection region and a first wire that extends between the first chip pad and the substrate. The first wire of an uppermost one of the first semiconductor chips is horizontally spaced apart from a lowermost one of the third semiconductor chips.