Offset Chip Stack Design for High Density Semiconductor Packages
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Solution Overview
Problem
Existing semiconductor packages face challenges in maximizing the number of embedded semiconductor chips within limited thickness and size constraints, requiring innovative stacking and support structures to maintain stability and prevent collapse.
Innovation Solution
A semiconductor package design featuring three chip stacks where the third chip stack is offset and supported by both the first and second chip stacks, with bonding fingers connecting the chips and an encapsulant filling the space between, creating a stable and compact structure that prevents collapse and allows for increased chip density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase capacity, then chip density is improved, but structural stability deteriorates due to collapse risk
Solution Approach 1:
The chip stack is divided into multiple segments with support structures inserted between adjacent semiconductor chips. Each support structure provides localized reinforcement at critical interfaces, segmenting the load path and preventing collapse while maintaining high chip density throughout the stack.
Solution Approach 2:
Support structures act as intermediary elements positioned between adjacent semiconductor chips in the stack. These intermediaries transfer and distribute mechanical loads, preventing direct contact and potential collapse of the chips while enabling the stack to maintain its structural integrity under compression.
2Quantity of substance
If chip stack height is increased to embed more chips, then chip density is improved, but device thickness is constrained
Solution Approach 1:
The support structures are nested within the chip stack assembly, with each support structure positioned in the interstitial space between adjacent semiconductor chips. This nesting approach allows the support structures to provide reinforcement without adding significant external dimensions, enabling high chip density within constrained package thickness.
Solution Approach 2:
Instead of increasing package thickness to accommodate more chips, the invention utilizes the vertical dimension within the existing thickness constraint by optimizing chip stacking arrangements and positioning support structures at critical intermediate levels, effectively using available space in the thickness dimension more efficiently.
3Stability of the object's composition
If support structures are added to prevent collapse, then structural stability is improved, but device complexity increases
Solution Approach 1:
Support structures are strategically positioned only at critical interfaces between adjacent semiconductor chips where collapse risk is highest, rather than uniformly throughout the entire stack. This localized approach provides necessary structural stability while minimizing the number of additional components and associated complexity.
Solution Approach 2:
The support structures are designed as simple, inexpensive components that can be easily manufactured and integrated into the chip stack. Their straightforward geometry and material requirements keep manufacturing complexity low while effectively providing the necessary mechanical support to prevent chip stack collapse.
Data Source
AI summary
A semiconductor package may include a first chip stack, a second chip stack, and a third chip stack. The third chip stack may include third semiconductor chips, the third chip stack coupled to both of the first and second chip stacks.