Offset Chip-Stacked Package With Bus Bar Heat Sink
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Solution Overview
Problem
Conventional chip-stacked package structures face challenges in increasing the scale of integrated circuits while minimizing occupied area and enhancing durability, particularly in effectively managing heat dissipation.
Innovation Solution
An offset chip-stacked package structure with a leadframe and bus bar is introduced, featuring a die pad exposed and a heat sink structure, where chips are stacked and electrically connected to inner leads, and the structure is encapsulated with outer leads extending out, allowing for improved heat dissipation and durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional chip-stacked package structures are used, then the scale of integrated circuits can be increased, but the occupied area cannot be minimized and heat dissipation is ineffective
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacking, arranging multiple chips vertically in layers rather than horizontally. This dimensional change allows multiple integrated circuits to be packaged in a compact volume, increasing the scale of integrated circuits while minimizing the occupied footprint area on the substrate.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked one on top of another, with each chip containing functional circuits. The chips are nested vertically within the package volume, allowing multiple independent integrated circuits to coexist in a compact space, thereby increasing circuit scale while reducing occupied area.
2Reliability
If conventional chip-stacked package structures are used, then chips can be connected electrically, but heat dissipation effectiveness is poor
Solution Approach 1:
The patent extracts the heat dissipation function from the conventional package structure by introducing dedicated heat dissipation components such as heat sinks or thermally conductive substrates. These components are separately integrated into the package to specifically address thermal management, allowing the electrical connection function to remain intact while improving heat dissipation effectiveness.
Solution Approach 2:
The package substrate serves multiple functions: it provides electrical connection pathways for the stacked chips and simultaneously acts as a heat dissipation structure through its thermal conductivity. This multi-functional design allows the same structural element to fulfill both electrical and thermal management requirements, improving heat dissipation without compromising electrical connection reliability.
3Area of stationary object
If chip thickness is reduced to minimize package size, then occupied area decreases, but structural durability is compromised
Solution Approach 1:
The patent employs composite material structures in the package substrate and interlayer materials, combining materials with different properties to achieve both thinness and strength. The composite structure provides mechanical support and durability even when individual layers are thin, allowing the package to maintain small size while ensuring structural integrity and durability.
Solution Approach 2:
The patent incorporates protective and cushioning structures within the package, such as protective coatings or buffer layers, that are designed in advance to prevent damage to the thin chip structures. This beforehand cushioning ensures that the reduced-thickness structure maintains adequate durability and resistance to mechanical stress throughout the package lifecycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the scale of integrated circuits, reduces thickness, and enhances durability by providing an effective heat sink surface, thus addressing the limitations of conventional chip-stacked structures.
Implementation Method 1
a heat sink structure is provided and so as to increase the durability of the offset chip-stacked structure
Data Source
AI summary
A stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, in which the die pad is provided between the inner leads and is vertically distant from the inner leads; a bus bar being provided between the inner leads and the die pad; an offset chip-stacked structure stacked by a plurality of chips, the offset chip-stacked structure being fixedly connected to a first surface of the die pad and electrically connected to the inner leads; and an encapsulant covering the offset chip-stacked structure, the inner leads, the first surface of die pad, and the upper surface of bus bar, the second surface of die pad and the lower surface of bus bar being exposed and the outer leads extending out of the encapsulant.