Offset Semiconductor Chip Stacks for High Density Low Thickness
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Solution Overview
Problem
Existing semiconductor package technologies face challenges in increasing memory capacity without increasing the thickness of the package, as stacking multiple chips leads to increased thickness and stability issues.
Innovation Solution
A semiconductor package design that includes two offset chip stacks supported by a third chip, with bonding wires connecting the chips to the package substrate, allowing for increased chip density without increasing the package thickness, and using a third chip to prevent the stacks from collapsing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase memory capacity, then the memory capacity is improved, but the package thickness increases
Solution Approach 1:
The patent transitions from a single vertical stack to a multi-dimensional arrangement with two offset chip stacks positioned side-by-side. This dimensional change allows chips to be organized in both vertical and lateral directions, increasing memory capacity while distributing the height requirement across multiple lower stacks rather than one tall stack, thereby reducing overall package thickness.
Solution Approach 2:
The patent divides the chip stack into multiple segments: first chip stack and second chip stack, each containing multiple chips offset from one another. This segmentation allows the total number of chips to be distributed across separate stacks that can be positioned at different heights, reducing the thickness requirement while maintaining high memory capacity through the combined chip count across all stacks.
2Quantity of substance
If multiple semiconductor chips are stacked to increase memory capacity, then the memory capacity is improved, but the structural stability deteriorates
Solution Approach 1:
The patent applies local quality by positioning the third chip specifically at the top of the first chip stack to provide targeted support. This localized structural reinforcement stabilizes the offset chip arrangement without requiring additional support structures throughout the entire package, maintaining structural integrity while preserving the high-density chip configuration.
Solution Approach 2:
The third chip acts as an intermediary element that bridges and supports the first chip stack. This intermediate component provides mechanical stability to the offset chip structure, preventing collapse while allowing the multiple chips in each stack to maintain their offset positions for high memory capacity.
3Quantity of substance
If chips are arranged in offset stacks to increase density, then the chip density is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetric offset arrangements within each chip stack, where chips are positioned at different lateral positions rather than perfectly aligned. This asymmetric design increases chip density by utilizing three-dimensional space more efficiently. The offset configuration, while geometrically complex, follows a systematic pattern that can be managed through standardized manufacturing processes for each stack unit.
Solution Approach 2:
The patent combines multiple chip stacks (first and second stacks) into a single integrated package structure. By merging these stacks and supporting them with a common third chip and shared bonding wire infrastructure, the manufacturing complexity is managed through modular assembly rather than creating entirely new complex structures, allowing offset high-density arrangements to be produced through coordinated manufacturing of standardized stack units.
Data Source
AI summary
A semiconductor package may include a first chip stack including first chips which are stacked on a package substrate. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate. The semiconductor package may include a third chip disposed on the first and second chip stacks.