Offset Chip Stack Underfill Layout for Smaller Reliable Packages
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving miniaturization and reliability, particularly in processing high-frequency signals while maintaining excellent electrical characteristics and a small size.
Innovation Solution
The semiconductor package design includes a substrate with stacked chip structures, where each chip stack has an adhesive layer and a chip protection structure, with an extension portion of the adhesive layer covering the chip protection structure and an underfill pattern that extends from the first chip stack to the second, providing enhanced protection and reducing the thickness of the adhesive layer to minimize package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the adhesive layer thickness is reduced to minimize package size, then the package size is reduced, but the reliability and stability of the chip stack may deteriorate
Solution Approach 1:
The underfill pattern extends in the horizontal direction (first direction) beyond the chip stack boundaries, providing lateral support and stress distribution in a different dimension. This allows the adhesive layer to be thinner while maintaining overall structural stability through the extended underfill structure.
Solution Approach 2:
The underfill structure is divided into multiple segments: the main underfill region within the chip stack and the extended underfill pattern outside the chip stack boundaries. This segmentation allows different regions to serve different functions - the main region provides vertical support while the extended region provides lateral stability.
2Adaptability or versatility
If multiple chip stacks are stacked to increase integration, then the functionality is improved, but the manufacturing complexity increases
Solution Approach 1:
The underfill pattern serves multiple functions simultaneously: it provides mechanical support for the chip stacks, enables electrical connections between stacked chips, and offers stress relief for the entire package structure. This multi-functionality reduces the need for additional separate components or processes.
Solution Approach 2:
The manufacturing process merges the underfill application with the chip stacking process itself. The underfill pattern is formed to extend beyond the chip stacks, allowing subsequent chips to be bonded directly to the extended underfill region, thereby combining multiple manufacturing steps into one integrated process.
3Reliability
If the underfill pattern extends beyond the chip stack to provide support, then the reliability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The underfill pattern is formed in advance with extensions that protrude beyond the chip stack boundaries before the chips are bonded. This preliminary formation of the extended underfill structure provides pre-positioned support regions that guide subsequent chip placement and bonding operations.
Solution Approach 2:
The extended underfill pattern acts as an intermediary structure between the substrate and the chip stacks. It provides a stable intermediate platform that facilitates precise chip positioning and bonding while compensating for potential misalignments.
Data Source
AI summary
A semiconductor package includes a substrate, a first chip stack on the substrate and including a first semiconductor chip, an underfill pattern on a first side of the first chip stack, and a second chip stack on the first chip stack and including a second semiconductor chip. The second chip stack is stacked so as to be offset to the first chip stack. The first chip stack includes a first adhesive layer under the first semiconductor chip and a first chip protection structure on the first semiconductor chip. The second chip stack includes a second adhesive layer under the second semiconductor chip and a second chip protection structure on the second semiconductor chip. An extension portion of the second adhesive layer is on one side of the first chip protection structure, and the underfill pattern extends from the first side of the first chip stack to the extension portion.