Offset Cancellation Circuit Using Switched Capacitor Gate Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional offset cancellation circuits for operational amplifiers face challenges in reducing random offset voltage, leading to increased power consumption, chip area, and manufacturing costs, especially in liquid crystal and organic EL display devices, where the variability of transistor characteristics causes significant issues.
Innovation Solution
An offset cancellation circuit is designed with a first active load connected to a differential pair, utilizing transistors and capacitances to store and manage offset voltage, allowing for high processing rates and accurate voltage output without increasing power consumption or chip area, by strategically controlling the connection states of transistors and capacitances during different time periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the capacitance of the capacitor is increased to reduce the influence of parasitic capacitance in offset cancellation circuits, then the offset voltage accuracy is improved, but the chip area increases and the processing rate is lowered
Solution Approach 1:
The patent applies preliminary action by storing the offset voltage in a capacitor during a dedicated offset storage period before the actual signal processing. The switch connects the capacitor to the differential amplifier inputs in advance, allowing the offset voltage to be captured and stored prior to affecting the signal path. This preliminary storage action enables accurate offset cancellation without requiring large capacitor values during signal processing.
Solution Approach 2:
The patent implements dynamics by using a switch to dynamically change the connection state of the capacitor between different operational phases. During the offset storage period, the switch connects the capacitor to the differential amplifier inputs for offset voltage storage. During the signal processing period, the switch disconnects the capacitor to prevent parasitic capacitance influence. This dynamic switching allows the system to achieve high offset accuracy with small capacitor values.
2Measurement precision
If the capacitance of the capacitor is increased to reduce the influence of parasitic capacitance, then the offset voltage accuracy is improved, but the processing rate is lowered
Solution Approach 1:
The offset voltage is stored in the capacitor during a dedicated offset storage period before signal processing begins. This preliminary action separates the offset cancellation function from the signal processing function in time, allowing small capacitor values to be used without compromising offset accuracy. The switch ensures the capacitor is only connected during the offset storage phase, not during signal processing.
Solution Approach 2:
The patent employs periodic action by alternating between an offset storage period and a signal processing period through switch control. During the offset storage period, the capacitor is connected to store offset voltage. During the signal processing period, the capacitor is disconnected to avoid affecting the signal. This periodic switching enables high processing rates while maintaining accurate offset cancellation with small capacitor values.
3Manufacturing precision
If conventional design techniques are used to reduce offset voltage, then the systematic offset voltage is reduced, but the random offset voltage caused by transistor variability remains
Solution Approach 1:
The patent extracts the offset voltage from the signal path by using a capacitor to store it separately during an offset storage period. The switch isolates the stored offset voltage from the differential amplifier inputs during signal processing, effectively taking out the offset component and preventing it from affecting the signal. This extraction approach addresses both systematic and random offset voltages without relying solely on transistor matching.
Solution Approach 2:
The capacitor acts as an intermediary element that stores the offset voltage separately from the signal path. During the offset storage period, the capacitor captures the offset voltage generated by transistor variability. During signal processing, the switch disconnects the capacitor, preventing this intermediary stored voltage from interfering with the signal while still enabling accurate offset cancellation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-accuracy, low-impedance output of input voltage with reduced power consumption and chip area, effectively addressing the limitations of existing circuits by minimizing the impact of transistor variability and improving processing rates in display devices.
Implementation Method 1
a first capacitance connected to the gate of the first transistor; a second capacitance connected to the gate of the second transistor
Data Source
AI summary
In an offset cancellation circuit according to the present invention, a first capacitance is connected to a gate of a first transistor of a first active load, and a second capacitance is connected to a gate of a second transistor of the first active load. A switch sets a first time period and a second time period in connection states between the first and second transistors and the first and second capacitances. The connection states between the first and second transistors and the first and second capacitances are set so that a gate voltage of the first transistor is supplied to the first capacitance, and a gate voltage of the second transistor is supplied to the second capacitance during the first time period; and so that the first and second capacitances can retain charges, and the second time period becomes an output time period of the operational amplifier during the second time period.