Offset Counter-Electrode Contact in SOI Transistors
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Solution Overview
Problem
The integration of field effect transistors with a counter-electrode on semiconductor on insulator substrates faces challenges due to increased parasite effects and complexity in fabrication, leading to larger dimensions and volume occupation, which complicates biasing conditions and integration.
Innovation Solution
A substrate configuration with an electrically conducting support substrate, an insulating layer, and a semiconductor material layer, featuring a counter-electrode in a portion of the support substrate and an insulating pattern that delineates an active area and a portion, with an electrically conducting contact passing through the pattern to connect the counter-electrode, allowing for reduced dimensions and simplified fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ground plane is integrated in the support substrate to control parasitic effects, then the control of short channel effect is improved, but the device complexity and fabrication difficulty increase due to additional contacts and insulating steps
Solution Approach 1:
The patent merges the counter-electrode contact with the source/drain electrode fabrication process. The same insulating pattern that defines the active area also serves to define the counter-electrode contact region, eliminating the need for separate insulating steps and contacts specifically for the counter-electrode.
Solution Approach 2:
The insulating pattern performs multiple functions: it defines the active area boundary, provides electrical isolation for the source/drain electrodes, and simultaneously defines the counter-electrode contact region. This multi-functionality reduces the overall device complexity while maintaining effective parasitic control.
2Reliability
If a ground plane is integrated in the support substrate to control parasitic effects, then the electric characteristics control is improved, but the device occupies larger surface area and volume
Solution Approach 1:
The patent utilizes the vertical dimension by having the insulating pattern extend down into the support substrate to define the counter-electrode contact region. This vertical integration allows the counter-electrode to be contacted through the insulating pattern without requiring additional lateral space, thus maintaining compact device footprint.
Solution Approach 2:
The counter-electrode contact structure is nested within the same insulating pattern that defines the active area. The insulating pattern creates a recess or region that accommodates the counter-electrode contact, effectively nesting multiple functional elements within the same lateral footprint.
3Reliability
If additional contacts are integrated for the counter-electrode, then the control of parasitic effects is improved, but the biasing conditions become more limited and complex
Solution Approach 1:
The patent combines the counter-electrode contact formation with the source/drain electrode fabrication steps. The insulating pattern is formed to simultaneously define both the active area and the counter-electrode contact region, allowing both electrodes to be contacted through the same fabrication process without additional biasing complexity.
Data Source
AI summary
The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.