Offset Current Constriction for Stable Mounting of Narrow Semiconductor Lasers

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Solution Overview

Problem

Semiconductor laser elements with inclined substrates face challenges in mounting on sub-mounts due to narrow widths, leading to potential tilting, falling, or breaking, which affects heat dissipation and polarization performance, increasing manufacturing costs and reducing reliability.

Innovation Solution

A semiconductor laser element with a substrate having inclined and vertical side faces, featuring a current constriction part offset from the center, allowing for stable mounting with reduced force application, ensuring proper solder wetting and preventing chip instability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the chip width is reduced to obtain more chips from a single wafer, then productivity increases, but the chip becomes unstable during mounting and may tilt, fall, collapse or break

Engineering Contradiction:
Improvenumber of chips per waferVSAvoidchip mounting stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces asymmetry by offsetting the current constriction part from the center of the substrate in the first direction. This creates an asymmetric structure where the center of gravity is shifted, allowing the chip to be mounted stably on the sub-mount despite the narrow width. The asymmetric positioning of the current constriction part relative to the electrode enables stable mounting without requiring excessive chip width.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If excessive load is applied to improve solder wettability, then the joining quality improves, but the narrow chip may tilt, fall, collapse or break

Engineering Contradiction:
Improvesolder wettabilityVSAvoidchip structural integrity
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The asymmetric offset of the current constriction part creates a configuration where the chip can be joined with appropriate load without excessive force. The offset positioning allows the joining load to be applied more effectively to the sub-mount interface rather than causing chip deformation, enabling good solder wettability while maintaining chip integrity.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent addresses the mounting stability issue by utilizing the first direction (perpendicular to the cavity direction) for offset positioning. This dimensional approach allows the current constriction part to be positioned offset from the center in the width direction while maintaining proper electrical and optical function, thereby enabling stable mounting without compromising chip strength.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Strength

If load is reduced to prevent chip tilting and breakage, then chip stability improves, but solder wettability decreases and heat dissipation drops

Engineering Contradiction:
Improvechip structural integrityVSAvoidheat dissipation performance
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The asymmetric offset configuration enables the chip to achieve both structural integrity and good solder wettability. The offset positioning of the current constriction part relative to the electrode creates a geometric relationship that allows moderate joining loads to effectively wet the solder while maintaining chip stability, avoiding both excessive force and insufficient bonding.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS9692204B2Semiconductor laser element and method of making semiconductor laser device
Publication Date: 2017.06.27 USHIO INC
  • US9692204B2 patent drawing
  • US9692204B2 patent drawing
  • US9692204B2 patent drawing

AI summary

A semiconductor laser element includes an inclined substrate, a semiconductor layer formed on one surface of the substrate, a first electrode (n-type electrode) formed on an opposite surface of the substrate, a second electrode (p-type electrode) formed on the semiconductor layer, and a current constriction part formed in the semiconductor layer. The semiconductor layer has a multi-layer structure including at least an active layer. The current constriction part causes a current to concentrate and flow to a particular area of the active layer. The first electrode or the second electrode is joined to a sub-mount. In one embodiment, the location of the current constriction part in a chip width direction is between the center of one of the first and second electrodes, which is joined to the sub-mount, and the center of the other electrode, which is not joined to the sub-mount, when viewed in the chip width direction.