Offset Delay Control for Multi-Level Bus Jitter Reduction
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Solution Overview
Problem
Multi-level communication architectures experience inherent jitter due to time shifts between symbol transitions, which reduces setup and hold times, leading to reduced robustness and reliability as clock speeds increase.
Innovation Solution
Output drivers apply offset delays to signal lines based on comparisons of current and next channel states, adjusting timing to reduce or eliminate jitter and maintain consistent transition times across symbol periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-level bus architectures are implemented to increase throughput, then data transfer speed is improved, but inherent jitter occurs between symbol transitions reducing setup and hold times
Solution Approach 1:
The patent applies preliminary action by calculating and applying offset delays to control signals before they are transmitted through the bus. The system determines the next channel state in advance, calculates the required offset delay based on this future state, and applies it to the control signal. This proactive timing adjustment compensates for the inherent jitter in multi-level signaling, ensuring that setup and hold times are maintained despite the variable transition magnitudes characteristic of multi-level bus architectures.
2Speed
If clock speeds are increased to improve processing performance, then system power and speed are improved, but the reduction of set-up and hold times leads to reduced robustness and reliability
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the timing parameters of control signals based on the channel state transitions. Instead of using fixed timing, the system calculates offset delays that vary depending on the current and next channel states. This allows the system to maintain reliable setup and hold times even at higher clock speeds, as the timing parameters are optimized for each specific transition scenario rather than being constrained by worst-case fixed timing.
Data Source
AI summary
Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures are disclosed herein. An example method may include comparing a current channel state of a channel of a multi-level communication bus with a next channel state of the channel. The example method may further include, based on the comparison, applying an offset delay to a control signal configured to control transition of a signal line of the channel from a value associated with the current channel state to a value associated with the next channel state. The example method may further include after application of the offset delay, driving the signal line to the value associated with the next channel state responsive to the control signal.