Digital Offset Detection Circuit for Glitch Attack Timing Anomalies
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuits are vulnerable to glitch attacks, which exploit variations in logic speed relative to the internal clock frequency, posing a security threat, and current defense mechanisms are power-intensive and tailored specifically to each circuit, making them costly and inflexible.
Innovation Solution
A circuit portion comprising a signal generator, delay introduction, edge-travel detector, and mask block to monitor and compare the timing of logic transitions against expected delays, allowing detection of abnormal delays indicative of attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analogue devices are used to monitor supply voltage or temperature to detect glitch attacks, then detection capability is improved, but power consumption increases and manufacturing cost increases
Solution Approach 1:
The patent replaces analogue monitoring devices with a digital logic-based detection circuit. The circuit uses digital signals and logic operations (XNOR gates, flip-flops, counters) to detect timing anomalies instead of using analogue voltage or temperature sensors. This substitution reduces power consumption while maintaining detection capability.
Solution Approach 2:
The patent creates a digital model of expected signal timing behavior and compares actual signal timing against this model. By copying the expected timing pattern into the detection circuit and using digital comparison, the system achieves reliable detection without the power costs of analogue monitoring.
2Reliability
If analogue devices are used to monitor supply voltage or temperature to detect glitch attacks, then detection capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent designs a universal detection circuit that can be integrated into various digital logic circuits regardless of their specific function. The same basic detection architecture (edge-travel detector, timing comparator, counter) can monitor different circuits by simply changing the target signal, eliminating the need for custom analogue monitoring designs for each circuit and reducing manufacturing costs.
Solution Approach 2:
Replacing custom analogue monitoring circuits with a standardized digital detection block simplifies the manufacturing process. The digital circuit can be synthesized using standard cell libraries and integrated more easily than custom analogue designs, reducing both development and production costs.
3Reliability
If analogue defence designs are used to detect glitch attacks, then detection capability is improved, but the design must be tailored specifically to each integrated circuit, increasing complexity
Solution Approach 1:
The detection circuit is designed to be universally applicable to different digital logic circuits. By monitoring the timing of logic transitions in the target circuit and comparing against expected timing, the same detection architecture can protect various circuits without requiring custom design for each application, reducing overall system complexity.
Solution Approach 2:
The detection circuit automatically adapts to the target circuit by monitoring its logic transitions and learning expected timing patterns during normal operation. This self-adjusting capability eliminates the need for manual tailoring of detection parameters for each circuit, simplifying the design process while maintaining detection effectiveness.
Data Source
AI summary
A circuit portion comprises a signal generator, clocked by a clock signal, for generating an alternating logic signal comprising a repeated sequence of alternating logic transitions. A circuit sub-portion introduces a delay to the alternating logic signal. An edge-travel detector samples the delayed alternating logic signal and outputs an edge-travel signal representative of a timing of a logic transition in the alternating logic signal with respect to the clock signal. A mask block compares the edge-travel signal with a mask signal to determine whether the timing of the logic transition matches one or more candidate timings, and outputs a comparison signal in dependence on this determination.