Offset Drain GAAFET Structure for Higher-Voltage Operation
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Solution Overview
Problem
Existing semiconductor devices face challenges in operating at higher voltages without causing performance deterioration or component damage, particularly in gate-all-around field-effect transistor (GAAFET) devices, due to the formation of the source, gate, and drain in the same plane.
Innovation Solution
The semiconductor device structure incorporates a drain formed in a separate plane from the source and gate, allowing for increased drain area and reduced resistance, enabling operation at voltages between 1.2 volts to 3.3 volts without component deterioration, using nanosheet channels and epitaxial layers for improved conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source, gate, and drain are formed in the same plane in conventional GAAFET devices, then the device structure is simple and fabrication is easier, but the device cannot operate at higher voltages without performance deterioration or component damage
Solution Approach 1:
The patent applies dimensionality change by moving the drain from the same plane as the source and gate to a separate plane, creating a three-dimensional offset drain structure. This spatial reconfiguration allows the drain to be positioned in a different vertical or lateral plane relative to the source-gate assembly, enabling higher voltage operation without increasing planar footprint or significantly complicating fabrication processes.
2Power
If the drain area is increased to reduce resistance, then the drive current improves, but the device footprint increases
Solution Approach 1:
The offset drain structure utilizes three-dimensional space by positioning the drain in a separate plane from the source and gate. This allows the drain area to be expanded in the vertical or lateral dimension without proportionally increasing the planar footprint, thereby reducing resistance and improving drive current while maintaining a compact device layout.
Solution Approach 2:
The drain structure is nested within or adjacent to the existing source-gate configuration in three-dimensional space. The offset drain can be positioned to overlap or abut the source region vertically or laterally, allowing the drain area to be effectively increased without occupying additional planar space, thus improving power characteristics without expanding device footprint.
Data Source
AI summary
A semiconductor device such as, for example, a gate-all-around field-effect transistor (GAAFET) device suitable for operability under higher operating voltage conditions (e.g., 1.2 volts to 3.3 volts). The semiconductor device includes a first channel that is formed in a first plane of the semiconductor device, a second channel that is formed in a second plane of the semiconductor device different from the first plane, a drain that is formed around the first channel, a gate that is formed around the second channel, and a source that is formed around the second channel.