Offset Field Plate GaN HEMT for Source-Side Field Control
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Solution Overview
Problem
GaN-based High Electron Mobility Transistors (HEMTs) with gate-to-drain field plates face reliability issues, particularly at class C operation due to significant electric fields on the source side of the gate, leading to poor performance in high power and high frequency applications.
Innovation Solution
A transistor device design featuring a field plate laterally offset from the gate, with a source-side wing portion extending from the central portion of the field plate, which reduces gate-to-drain capacitance and enhances reliability by minimizing the electric field on the source side, thereby improving breakdown voltage and reducing high-field trapping effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a gate-to-drain field plate is used in GaN-based HEMTs, then breakdown voltage is increased and high-field trapping effects are reduced, but reliability deteriorates due to significant electric fields on the source side of the gate
Solution Approach 1:
The field plate is segmented into two distinct portions: a first field plate portion positioned over the drain side of the channel and a second field plate portion positioned over the source side of the channel. This segmentation allows independent optimization of each portion's function, enabling the first portion to provide breakdown voltage enhancement while the second portion controls electric field distribution to protect reliability
Solution Approach 2:
Different regions of the field plate are given different characteristics through the segmentation. The first field plate portion (drain side) is optimized for withstanding high electric fields and increasing breakdown voltage, while the second field plate portion (source side) is optimized for controlling and reducing electric field concentration to prevent reliability degradation. Each portion has localized quality tailored to its specific functional requirement
2Productivity
If a conventional field plate design is used, then device performance is improved at microwave frequencies, but poor reliability performance occurs at class C operation due to significant electric fields on the source side
Solution Approach 1:
The field plate is divided into two functional segments: the first portion maintains performance benefits at microwave frequencies by providing gate-to-drain capacitance reduction, while the second portion specifically addresses class C operation reliability by controlling source-side electric fields. This segmentation enables simultaneous optimization for both performance and reliability under different operating conditions
3Use of energy by moving object
If the field plate is positioned directly over the channel, then gate-to-drain capacitance is reduced, but electric field concentration on the source side increases leading to reliability issues
Solution Approach 1:
The field plate structure is segmented into a first portion extending over the drain side and a second portion extending over the source side. The second portion is specifically positioned and dimensioned to reduce electric field concentration at the source side of the gate without compromising the capacitance reduction benefit provided by the first portion. This segmentation enables independent optimization of electric field management and capacitance characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a minimum noise figure of less than 3.4 across a range of frequencies from 0.3 GHz to 26 GHz, peak power added efficiency greater than 60% at 50V gate voltage, and a predicted lifetime of over 106 hours at 225°C junction temperature, while maintaining high output power and reliability.
Implementation Method 1
This can result in a reduction of the electric field on the gate-to-drain side of the transistor, thereby increasing breakdown voltage and reducing the high-field trapping effect
Implementation Method 2
The 2DEG is an accumulation layer in the undoped smaller bandgap material and can contain a relatively high sheet electron concentration, for example, in excess of 10^13 carriers/cm^2
Implementation Method 3
electrons that originate in the wider bandgap semiconductor may transfer to the 2DEG, allowing a relatively high electron mobility due to reduced ionized impurity scattering
Data Source
AI summary
A transistor device may include a semiconductor structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer; a source contact and a drain contact on the barrier layer; a gate contact on the semiconductor structure between the source contact and the drain contact, the gate contact including a drain-side wing portion extending from a central portion of the gate contact; and a field plate on the semiconductor structure between the gate contact and the drain contact and laterally offset from the gate contact by a distance. The field plate may include a first wing portion extending from a central portion of the field plate.