Offset Gate Bus Contact for Power Semiconductor Reliability
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Solution Overview
Problem
Power semiconductor devices face issues with leakage current and premature failure due to electric field crowding and concentration, particularly at the edges of the active region, which can lead to avalanche breakdown and increased current flow.
Innovation Solution
The semiconductor device incorporates a gate trench structure with a gate finger extending below the surface and a gate bus that is electrically connected via a vertical via offset from the end of the gate finger, reducing electrical field concentration and improving the distribution of the gate signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate bus is directly connected to the end of the gate finger, then the electrical connection is simple and direct, but electric field crowding and concentration occur at the edge of the active region leading to leakage current and premature failure
Solution Approach 1:
The patent applies local quality by creating different connection configurations in different regions. The offset connection position creates a localized change in the electric field distribution pattern, reducing field concentration at specific critical points while maintaining overall device functionality. This localized structural modification addresses the reliability issue without requiring complete redesign of the entire gate structure.
Solution Approach 2:
The offset connection acts as an intermediary configuration between the gate bus and gate finger, modifying the direct connection path. By introducing this intermediate offset position, the patent mediates the electric field interaction between the gate structures, preventing direct field concentration at the edge while still achieving electrical connection. This intermediary approach resolves the contradiction between simple connection and reliable operation.
2Manufacturing precision
If the gate finger extends deep below the surface to improve gate control, then the gate control over the channel is enhanced, but the manufacturing complexity and difficulty increase
Solution Approach 1:
The patent addresses manufacturing challenges by optimizing the gate finger extension depth and connection geometry in the vertical dimension. By carefully controlling the offset connection position and gate finger depth, the patent achieves effective gate control while managing the complexity of trench fabrication. This dimensional optimization allows precise gate control without proportionally increasing manufacturing difficulty.
Solution Approach 2:
The patent applies parameter changes by optimizing specific geometric parameters including gate finger depth, offset distance, and connection dimensions. By adjusting these parameters within optimal ranges, the patent achieves the desired gate control precision while keeping manufacturing processes feasible. The offset connection parameters are specifically tuned to balance control effectiveness with manufacturing ease.
3Reliability
If the gate bus is positioned to reduce electric field concentration, then leakage current is reduced and reliability improves, but the gate signal distribution may become less efficient
Solution Approach 1:
The patent applies partial action by implementing an offset connection that provides sufficient gate signal distribution without requiring direct end-to-end alignment. The offset position is carefully chosen to provide just enough separation to reduce field concentration while maintaining adequate signal coupling. This partial offset achieves the necessary reliability improvement without excessively compromising signal distribution efficiency.
Solution Approach 2:
The offset connection configuration works to create more uniform electric field distribution across the gate structure, approaching equipotential conditions in the critical regions. By reducing field concentration through the offset position, the patent creates a more balanced potential distribution that prevents premature breakdown while still allowing effective gate control and signal distribution across the active region.
Data Source
AI summary
Power switching devices include a semiconductor layer structure, a unit cell transistor comprising a gate finger, the gate finger extending in a first direction in a gate trench that is below a surface of the semiconductor layer structure, and a gate bus, wherein a portion of the gate bus vertically overlaps the gate finger and is electrically connected to the gate finger.