Offset Gate LDMOS With Stacked JFETs For E-Field Control
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Solution Overview
Problem
High-voltage LDMOS devices face challenges in reducing surface E-field peaks and on resistance while requiring a simplified manufacturing process, as existing designs are complex and inefficient in achieving the necessary breakdown voltage and device size reduction.
Innovation Solution
The implementation of an offset gate structure and stacked junction field effect transistors (JFETs) in the drift region, along with an epitaxial refill process to create alternating conductivity pillars, reduces surface E-field peaks and increases breakdown voltage by directing current flow deeper into the semiconductor bulk, thereby simplifying the device design and reducing on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS structure with gate between source and drain is used, then device can operate in on state with current flow, but surface E-field peaks are high and breakdown voltage is insufficient
Solution Approach 1:
The gate is positioned asymmetrically offset from the center of the source region, specifically on the source side away from the drain. This asymmetric positioning shifts the channel formation location away from the high-field drain region, reducing surface E-field peaks at the drain-gate interface while maintaining effective current control. The offset gate structure creates an asymmetric electric field distribution that lowers peak fields and increases breakdown voltage.
Solution Approach 2:
The invention introduces a lateral offset dimension to the traditional vertical gate alignment. Instead of the gate being directly above the source-drain path, it is shifted laterally by an offset distance. This dimensional change redirects current flow deeper into the drift region bulk rather than concentrating it at the surface, thereby reducing surface E-field peaks and increasing breakdown voltage.
2Ease of manufacture
If drift region structure is simplified to reduce manufacturing complexity, then fabrication process becomes easier, but device performance in controlling E-field and resistance may deteriorate
Solution Approach 1:
The offset gate structure serves multiple functions simultaneously: it defines the channel region, controls current flow, and reduces surface E-field peaks. By positioning the gate offset from the source-drain centerline, a single structural modification achieves both device control and E-field management, eliminating the need for separate complex E-field reduction structures and simplifying the overall fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces surface E-field peaks, increases breakdown voltage, and simplifies the manufacturing process, resulting in a high-voltage LDMOS device with improved performance and reduced on-state resistance, suitable for advanced technology integration.
Implementation Method 1
the surface E-field 38 has peaks 40 and 42 of drift region ND and a plateau 44 between peaks 40, 42
Implementation Method 2
filling said trenches by segment epitaxial refill with material of said first conductivity type, resulting in alternating pillars of said first and second conductivity type
Data Source
AI summary
A semiconductor device, such as a LDMOS device, comprising: a semiconductor substrate; a drain region in the semiconductor substrate; a source region in the semiconductor substrate laterally spaced from the drain region; and a drift region in the semiconductor substrate between the drain region and the source region. A gate is operatively coupled to the source region and is located offset from the drain region on a side of the source region opposite from the drain region. When the device is in an on state, current tends to flow deeper into the drift region to the offset gate, rather than near the device surface. The drift region preferably includes at least first and second stacked JFETs. The first and second stacked JFETs include first, second and third layers of a first conductivity type, a fourth layer intermediate the first and second layers including alternating pillars of the first conductivity type and of a second conductivity type extending between the source and drain regions; and a fifth layer intermediate the second and third layers, including alternating pillars of the first and second conductivity types extending between the source and drain regions.