Offset Guard Ring Structure for Higher Breakdown Semiconductor Devices

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving high breakdown voltage and reducing loss due to the limited ability to narrow the interval between guard rings, which affects the depletion layer spread and concentration of the drift region.

Innovation Solution

The semiconductor device incorporates a semiconductor layer with a drift region, lower guard rings, and upper guard rings of different conductivity levels, where the lower guard rings are offset relative to the upper guard rings, allowing for a smaller minimum interval between adjacent guard rings, thereby enhancing the depletion layer spread and breakdown voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the interval between guard rings is narrowed to improve depletion layer spread and breakdown voltage, then the breakdown voltage is improved, but the manufacturing complexity increases due to the need for dedicated ion implantation processes

Engineering Contradiction:
Improvebreakdown voltageVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the formation of lower and upper guard rings into a single ion implantation process. The lower guard rings are formed by ion implantation through a first mask, and the upper guard rings are formed by ion implantation through a second mask, both using the same dedicated ion implantation equipment and process conditions. This merging of processes reduces manufacturing complexity while achieving the narrow interval between guard rings needed for improved breakdown voltage.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a vertical dimension by forming guard rings at different depth ranges within the semiconductor layer. The lower guard rings are formed in a first depth range and the upper guard rings are formed in a second depth range, creating a three-dimensional guard ring structure. This dimensional approach allows the guard rings to be spaced closer together horizontally while maintaining adequate vertical separation, improving breakdown voltage without excessive manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the interval between guard rings is reduced to enhance depletion layer spread, then the depletion layer spread is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvedepletion layer spreadVSAvoidguard ring positioning precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent segments the guard ring structure into lower and upper components at different depth ranges. The lower guard rings extend from the surface to a first depth, while the upper guard rings extend from the surface to a second depth greater than the first depth. This segmentation allows each guard ring type to be formed with optimized ion implantation parameters, reducing the precision requirements for overall guard ring positioning while achieving improved depletion layer spread.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by forming lower and upper guard rings with different conductivity types and concentrations at different depth ranges. The lower guard rings have a first conductivity type with a first concentration, while the upper guard rings have a second conductivity type with a second concentration. This local differentiation allows each region to be optimized for its specific function, reducing the overall manufacturing precision requirements while enhancing depletion layer spread.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240170567A1Semiconductor device
Publication Date: 2024.05.23 DENSO CORP
  • US20240170567A1 patent drawing
  • US20240170567A1 patent drawing
  • US20240170567A1 patent drawing

AI summary

A semiconductor device includes lower guard rings and upper guard rings. An upper portion of each of the lower guard rings overlaps a lower portion of the corresponding upper guard ring. A lower inner peripheral surface of each of the lower guard rings is offset to one side in a predetermined direction with respect to an upper inner peripheral surface of the corresponding upper guard ring. A lower outer peripheral surface of each of the lower guard rings is offset to the one side in the predetermined direction with respect to an upper outer peripheral surface of the corresponding upper guard ring.