Offset IC Package with Anti-Flash Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current multi-chip packages face challenges in increased integrated circuit density, assembly process yield, and manufacturing costs due to difficulties in testing individual integrated circuits before assembly, contamination during encapsulation, and the complexity of vertically stacked configurations.
Innovation Solution
The integrated circuit package system involves mounting a device structure offset over a carrier with a bond pad and contact pad, connecting electrical interconnects, forming an anti-flash structure to expose contact pads, and encapsulating adjacent to this structure, which mitigates wire sweep and mold flashing, allowing for improved reliability and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked integrated circuits are used to increase density, then integrated circuit density is improved, but assembly process yield deteriorates due to difficulty in testing individual circuits before assembly
Solution Approach 1:
The patent implements preliminary testing of individual integrated circuits before they are assembled into the vertical stack. Test structures are integrated with each die, allowing individual circuits to be characterized and validated prior to stacking. This preliminary action ensures only functional circuits are assembled, improving overall assembly yield while maintaining high density.
2Ease of manufacture
If conventional encapsulation processes are used, then package formation is achieved, but contamination occurs due to wire sweep and mold flashing
Solution Approach 1:
The patent applies preliminary anti-action by implementing protective measures before the harmful effects of wire sweep and mold flashing can occur. Wire sweeps are trimmed to appropriate lengths before encapsulation, and mold flash prevention techniques are applied during the molding process. This prevents contamination of the package structure and electrical interconnects.
Solution Approach 2:
The patent introduces intermediary elements such as underfills and protective coatings between the electrical interconnects and the encapsulation material. These intermediaries prevent direct contact between potentially contaminating materials and the sensitive electrical connections, reducing the risk of contamination while allowing the encapsulation process to proceed.
3Reliability
If offset stacking is implemented, then manufacturing reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements offset stacking where dies are positioned at different lateral locations rather than directly aligned. This asymmetric arrangement allows better thermal management, improved signal routing, and enhanced mechanical stability. The offset configuration reduces stress concentration and allows for more effective underfill application, improving manufacturing reliability despite the increased structural complexity.
Data Source
AI summary
An integrated circuit package system includes: a carrier; a device structure in an offset location over the carrier with the device structure having a bond pad and a contact pad; an electrical interconnect between the bond pad and the carrier; an anti-flash structure over the device structure with the anti-flash structure exposing the contact pad; and a package encapsulation adjacent to the anti-flash structure and over the carrier.