Offset Conductive Interconnect Layout for Multi-Deck Memory Alignment
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Solution Overview
Problem
Existing technologies face challenges in accurately landing conductive interconnects between circuitry levels due to upward projections, leading to misalignment and impaired device performance.
Innovation Solution
Implementing conductive interconnects that are laterally offset relative to one another, avoiding direct alignment issues and ensuring proper coupling between circuitry levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive interconnects are vertically aligned between levels, then direct electrical coupling is achieved, but upward projections cause misalignment and contorted shapes during patterning
Solution Approach 1:
The patent transitions from vertical alignment (single dimension) to lateral offset alignment (introducing horizontal dimension). Conductive interconnects at different levels are positioned at different lateral locations rather than directly above each other, eliminating the projection problem while maintaining electrical coupling through the offset configuration.
Solution Approach 2:
The patent introduces asymmetric lateral positioning of conductive interconnects between levels. Instead of symmetric vertical alignment, interconnects are deliberately offset in lateral positions, creating an asymmetric configuration that prevents the formation of contorted shapes during patterning while ensuring proper electrical coupling.
2Manufacturing precision
If conductive interconnects are laterally offset, then misalignment is prevented, but direct vertical coupling path is interrupted
Solution Approach 1:
The patent introduces conductive structures at intermediate lateral positions that serve as mediators between offset interconnects. These intermediate structures facilitate the electrical coupling path, allowing laterally offset interconnects to communicate electrically without requiring direct vertical alignment, thus maintaining simplicity while achieving precision.
Data Source
AI summary
Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.