Offset Memory Module Units for Signal Integrity
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Solution Overview
Problem
Increasing memory capacity in memory modules leads to more complex and longer wirings on printed circuit boards, which can compromise operating speed.
Innovation Solution
A memory module set design where memory module units are spaced and offset relative to each other on a substrate, allowing for a simpler layout of electrical wirings and maintaining consistent wire lengths, thereby preventing signal distortion and optimizing memory operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased by mounting more memory chips on the PCB, then memory capacity is improved, but wiring complexity and length increase, compromising operating speed
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of memory modules to a three-dimensional stacked configuration. Memory modules are vertically stacked and interconnected through through-substrate vias, enabling increased memory capacity without expanding the horizontal PCB footprint. This vertical dimensionality change reduces wiring length and complexity while maintaining high memory capacity.
Solution Approach 2:
The patent implements a nested structure where multiple memory modules are stacked vertically within a compact PCB footprint. Each memory module in the stack is interconnected through through-substrate vias that pass through intermediate layers, creating a nested arrangement that maximizes memory capacity within a limited space while minimizing external wiring complexity.
2Quantity of substance
If more memory chips are mounted on the PCB to increase capacity, then memory capacity is improved, but wire length increases causing signal distortion
Solution Approach 1:
The patent utilizes vertical stacking to reduce horizontal wire lengths. Memory modules are positioned in a three-dimensional stack with interconnections through through-substrate vias, significantly shortening the signal path compared to traditional planar arrangements. This dimensional transition reduces wire length and associated signal distortion while maintaining high memory capacity.
3Quantity of substance
If memory module density is increased, then memory capacity is improved, but signal transmission quality deteriorates due to longer wirings
Solution Approach 1:
The patent employs vertical stacking with through-substrate via interconnections to reduce signal path length and improve transmission quality. The three-dimensional arrangement minimizes wiring length while maintaining high memory density, thereby preserving signal integrity and transmission reliability even as capacity increases.
4Area of stationary object
If memory modules are arranged in a compact layout, then space utilization is improved, but wiring complexity increases
Solution Approach 1:
The patent implements a nested vertical stacking arrangement where memory modules are positioned one above another within a compact PCB footprint. Through-substrate vias provide interconnections between stacked modules, enabling high space utilization while keeping wiring complexity manageable through standardized vertical interconnection patterns rather than complex horizontal routing.
Solution Approach 2:
The patent resolves the conflict between compact layout and wiring complexity by transitioning to three-dimensional stacking. This vertical arrangement maximizes PCB area utilization while simplifying wiring topology through standardized via-based interconnections, avoiding the need for complex horizontal routing patterns.
Data Source
AI summary
A memory module set includes a main integrated circuit (IC) for transmitting and receiving an electrical signal, a first group of memory modules including at least one memory module having a first pin unit connected to the main IC, and a second group of memory modules including at least one memory module having a second pin unit connected to the main IC. The groups of memory modules and the main IC are arrayed in a first direction on a substrate, and the second group of memory modules is offset with respect to the first group of memory modules in a second direction that is perpendicular to the first direction so as to have a position relative to the main IC in the second direction that is different from that of the first group of memory modules.