Offset 3D Memory Cell Blocks for Wiring Resistance Reduction
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Solution Overview
Problem
Memory devices with a 3D cross-point structure face increased wiring resistance and larger footprints due to wiring connections being outside the cell blocks, leading to higher integration density challenges.
Innovation Solution
The memory device design includes offset cell blocks, where bit lines and word lines are routed within the footprint of the cell blocks, reducing wiring resistance and overall device size by confining the wiring connections within the cell block perimeter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are stacked in two or more layers with wiring connections outside cell blocks, then integration density increases, but wiring resistance and device footprint increase
Solution Approach 1:
The patent transitions from planar wiring connections to three-dimensional wiring connections by routing bit lines through vertical vias between stacked cell blocks. This dimensional change allows wiring to pass through the interior of the stacked structure rather than around the exterior, reducing wiring length and resistance while maintaining high integration density.
Solution Approach 2:
The patent implements nested wiring by routing bit lines through the interior of stacked cell blocks. The wiring structure is embedded within the cell block stack, with bit line contacts positioned at different vertical levels to connect to memory cells in respective cell blocks, creating a nested configuration that reduces external wiring footprint.
2Quantity of substance
If memory devices are stacked in two or more layers with wiring connections outside cell blocks, then integration density increases, but device footprint increases
Solution Approach 1:
The patent utilizes vertical dimension for wiring connections by routing bit lines through vias between stacked cell blocks. This moves wiring from the horizontal plane to the vertical dimension, allowing the device footprint to remain compact while accommodating multiple layers of memory cells with efficient interconnections.
Solution Approach 2:
The wiring structure is nested within the cell block stack, with bit line contacts and interconnects positioned inside the footprint of the cell blocks. This nested arrangement eliminates the need for external wiring regions, reducing the overall device footprint while maintaining high integration density.
3Quantity of substance
If cell blocks are arranged in stacked configuration, then integration density increases, but wiring connection area increases
Solution Approach 1:
The patent routes bit lines vertically through the stacked cell blocks using vias, transforming the wiring connection from a horizontal expansion to a vertical penetration. This dimensional change allows multiple cell blocks to be interconnected through a compact wiring area at each vertical level, reducing the total wiring connection area.
Solution Approach 2:
The bit line contacts and wiring structures are nested within the cell block footprints, with wiring connections positioned inside the boundary of the cell blocks rather than outside. This nested configuration minimizes the wiring connection area by utilizing the vertical space within the cell block stack.
Data Source
AI summary
A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.